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Freescale Semiconductor Technical Data
Document Number: MM908E621 Rev. 5.0, 6/2008
Integrated Quad Half-bridge and Triple High Side with Embedded MCU and LIN for High End Mirror
The 908E621 is an integrated single package solution that includes a high performance HC08 microcontroller with a SMARTMOSTM analog control IC. The HC08 includes flash memory, a timer, enhanced serial communications interface (ESCI), a 10 bit analog-to-digital converter (ADC), serial peripheral interface (SPI) (only internal), and an internal clock generator module (ICG). The analog control die provides four half-bridge and three high side outputs with diagnostic functions, a Hall-effect sensor input, analog inputs, voltage regulator, window watchdog, and local interconnect network (LIN) physical layer. The single package solution, together with LIN, provides optimal application performance adjustments and space saving PCB design. It is well suited for the control of automotive high end mirrors. Features * * * * * * * * * * High performance M68HC908EY16 core 16K bytes of on-chip flash memory, 512 bytes of RAM Two 16-bit, 2-channel timers LIN physical layer interface Autonomous MCU watchdog / MCU supervision One analog input with switchable current source Four low RDS(ON) half-bridge outputs Three low RDS(ON) high side outputs Wake-up and 2/3-pin hall-effect sensor input 12 microcontroller I/Os
>22F 100nF
908E621
QUAD HALF-BRIDGE AND TRIPLE HIGH SIDE SWITCH WITH EMBEDDED MCU AND LIN
DWB SUFFIX 98ASA10712D 54-PIN SOICW-EP
ORDERING INFORMATION
Device MM908E621ACDWB/R2 Temperature Range (TA) -40C to 85C Package 54 SOICW-EP
LIN
VSUP[1:8]
L0
Wake Up Input
VDDA/VREFH EVDD VDD
4,7F 100nF
HB1 HB2
M M 4 x Half Bridge Outputs
VSSA/VREFL EVSS VSS RST_A RST IRQ_A IRQ PTA0/KBD0 PTA1/KBD1 PTA2/KBD2 PTA3/KBD3 PTA4/KBD4 PTB3/AD3 PTB4/AD4 PTB5/AD5 PTC2/MCLK PTC3/OSC2 PTC4/OSC1
HB3
M
HB4 HS1 HS2 HS3
High Side Output 1 High Side Output 2 High Side Output 3
C PortA
C PortB
C PortC
Internally connected
HVDD A0 A0CST H0
Switched 5V output Analog Input with current source Analog Input current source trim 2-/3-pin hall sensor input Pull to ground for user mode
C PortD
Internally connected
PTD0/TACH0 PTD1/TACH1 PTE1/RxD GND[1:4] EP
C PortE
TESTMODE
Figure 1. 908E621 Simplified Application Diagram
Freescale Semiconductor, Inc. reserves the right to change the detail specifications, as may be required, to permit improvements in the design of its products.
(c) Freescale Semiconductor, Inc., 2007-2008. All rights reserved.
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VSSA/VREFL EVSS IRQ GND[1:4] VSUP[1:8] TESTMODE RST_A IRQ_A PTD0/TACH0 PTE1/RXD RST LIN Single Breakpoint Break Module Voltage Regulator PTE1/RXD PTE0/TXD TXD LIN Physical Layer Wakeup Port Reset Control High Side Driver & Diagnostic Switched VDD Driver & Diagnostic RXD 5-Bit Keyboard Interrupt Module 2-channel Timer Interface Module A 2-channel Timer Interface Module B Enhanced Serial Communication Interface Module Autonomous Watchdog Computer Operating Properly Module Serial Peripheral Interface Module Configuration Register Module Periodic Wake-up Timebase Module Arbiter Module Prescaler Module PTC1/MOSI Security Module BEMF Module PTA5/SPSCK PTC0/MISO PTA6/SS MISO MOSI SPSCK SS PTD0/TACH0 PWM HB2 Half Bridge Driver & Diagnostic VSS VDD HVDD L0 HS1[a:b] High Side Driver & Diagnostic HS2 High Side Driver & Diagnostic HS3 Internal Bus 24 Integral System Integration Module Single External IRQ Module Half Bridge Driver & Diagnostic HB1 Power-ON Reset Module SPI & CONTROL
908E621
EVDD
INTERNAL BLOCK DIAGRAM
VDDA/VREFH
M68HC08 CPU CPU ALU Registers
PTA0/KBD0
Control and Status Register, 64 Bytes User Flash, 15,872 Bytes User RAM, 512 Bytes Monitor ROM, 310 Bytes Flash programming (Burn-in), ROM 1024 Bytes
PTA1/KBD1
User Flash Vector Space, 36 Bytes
PTA2/KBD2
OSC2 Internal Clock OSC1 Generator Module
PTA3/KBD3
RST
PTA4/KBD4
IRQ
PTB3/AD3
PTB4/AD4
VREFH VDDA 10 Bit Analog-toVREFL Digital Converter Module VSSA VDD POWER VSS
PTB5/AD5
INTERNAL BLOCK DIAGRAM
HB3
PTC2/MCLK
Half Bridge Driver & Diagnostic
PTC3/OSC2 PORT C DDRC DDRA PORT A PTC4/OSC1 PTC3/OSC2 PTC2/MCLK PTC1/MOSI PTC0/MISO PTD1/TACH1 PTD0/TACH0 PTE1/RXD PTE0/TXD
Half Bridge Driver & Diagnostic
HB4
PTC4/OSC1
PTD1/TACH1
FLSVPP DDRB PORT B
HALLPORT PTB0/AD0 ADOUT Analog Multiplexer
H0 A0 A0CST Analog Port with Current Source
PORT D PORT E DDRD DDRE
PTA6/SS PTA5/SPSCK PTA4/KBD4 PTA3/KBD3 PTA2/KBD2 PTA1/KBD1 PTA0/KBD0 PTB7/AD7/TBCH1 PTB6/AD6/TBCH0 PTB5/AD5 PTB4/AD4 PTB3/AD3 PTB2/AD2 PTB0/AD0 PTB0/AD0
Analog Integrated Circuit Device Data Freescale Semiconductor
Figure 2. 908E621 Simplified Internal Block Diagram
PIN CONNECTIONS
PIN CONNECTIONS
Transparent Top View of Package
PTC4/OSC1 PTC3/OSC2 PTC2/MCLK PTB5/AD5 PTB4/AD4 PTB3/AD3
IRQ RST
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
54 53 52 51 50 49 48 47 46 45 44 43 42
(PTD0/TACH0/BEMF -> PWM) PTD1/TACH1
RST_A IRQ_A
LIN A0CST A0 GND1 HB4 VSUP1 GND2 HB3 VSUP2 NC NC TESTMODE GND3 HB2 VSUP3
Exposed Pad
41 40 39 38 37 36 35 34 33 32 31 30 29 28
PTA0/KBD0 PTA1/KBD1 PTA2/KBD2 FLSVPP PTA3/KBD3 PTA4/KBD4 VDDA/VREFH EVDD EVSS VSSA/VREFL (PTE1/RXD <- RXD) VSS VDD HVDD L0 H0 HS3 VSUP8 HS2 VSUP7 HS1b HS1a VSUP6 VSUP5 GND4 HB1 VSUP4
Figure 3. Pin Connections Table 1. Pin Definitions A functional description of each pin can be found in the Functional Pin Description section beginning on page 21.
Die MCU Pin 1 2 3 4 5 6 7 8 9 Pin Name PTC4/OSC1 PTC3/OSC2 PTC2/MCLK PTB5/AD5 PTB4/AD4 PTB3/AD3
IRQ RST
Formal Name Port C I/Os
Definition These pins are special function, bidirectional I/O port pins that are shared with other functional modules in the MCU. These pins are special function, bidirectional I/O port pins that are shared with other functional modules in the MCU. This pin is an asynchronous external interrupt input pin. This pin is bidirectional, allowing a reset of the entire system. It is driven low when any internal reset source is asserted. This pin is the PWM signal test pin. It internally connects the MCU PTD0/TACH0 pin with the Analog die PWM input. Note: Do not connect in the application.
MCU
Port B I/Os
MCU MCU MCU / Analog
External Interrupt Input External Reset PWM signal
(PTD0/TACH0/BEMF -> PWM)
MCU MCU / Analog
10 44
PTD1/TACH1 (PTE1/RXD <- RXD)
Port D I/Os LIN Transceiver Output
This pin is a special function, bidirectional I/O port pin that is shared with other functional modules in the MCU. This pin is the LIN Transceiver output test pin. It internally connects the MCU PTE1/RXD pin with the Analog die LIN transceiver output pin RXD. Note: Do not connect in the application.
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PIN CONNECTIONS
Table 1. Pin Definitions (continued) A functional description of each pin can be found in the Functional Pin Description section beginning on page 21.
Die MCU Pin 45 48 MCU MCU 46 47 49 50 52 53 54 51 11 12 13 14 15 16 19 25 30 29 26 20 17 18 21 27 28 31 32 35 22 23 24 34 35 36 38 Analog 39 Pin Name VSSA/VREFL VDDA/VREFH EVSS EVDD PTA4/KBD4 PTA3/KBD3 PTA2/KBD2 PTA1/KBD1 PTA0/KBD0 FLSVPP
RST_A IRQ_A
Formal Name ADC Supply and Reference Pins MCU Power Supply Pins Port A I/Os
Definition These pins are the power supply and voltage reference pins for the analog-to-digital converter (ADC). These pins are the ground and power supply pins, respectively. The MCU operates from a single power supply. These pins are special function, bidirectional I/O port pins that are shared with other functional modules in the MCU.
MCU Analog Analog Analog Analog Analog Analog
Test Pin Internal Reset Internal Interrupt Output LIN Bus Analog Input Trim Pin Analog Input Pin Power Ground Pins
For test purposes only. Do not connect in the application. This pin is the bidirectional reset pin of the analog die. This pin is the interrupt output pin of the analog die indicating errors or wake-up events. This pin represents the single wire bus transmitter and receiver. This is the analog input trim pin for the A0 input. This is to connect a known fixed resistor value to trim the current source measurement. This pin is an analog input port with selectable source values. These pins are device power ground connections.
LIN A0CST A0 GND1 GND2 GND3 GND4 HB1 HB2 HB3 HB4 VSUP1 VSUP2 VSUP3 VSUP4 VSUP5 VSUP6 VSUP7 NC NC TESTMODE HS1a HS1b HS2 HS3 H0
Analog
Half-bridge Outputs
This device includes power MOSFETs configured as four half-bridge driver outputs. These outputs may be configured for DC motor drivers, or as high side and low side switches. Note: The HB3 and HB4 have a lower RDS(ON) then HB1 and HB2.
Analog
Power Supply Pins
These pins are device power supply pins.
- Analog Analog Analog
No Connect TESTMODE Input
These pins are not connected. Pin for test purpose only. In application this pin needs to be tied GND.
High Side HS1 Output This output pin is a low RDS(ON) high side switch. High Side HS2 Output These output pins are low RDS(ON) high side switches. High Side HS3 Output Hall-Effect Sensor / General Purpose Input Wake-up Input Switchable VDD Output Voltage Regulator Output This pin provides an input for a Hall-effect sensor or general purpose input. This pin provides an high voltage input, which is wake-up capable. This pin is a switchable VDD output for driving resistive loads requiring a regulated 5.0V supply; e.g. potentiometers. The +5.0V voltage regulator output pin is intended to supply the embedded microcontroller.
Analog Analog
40 41
L0 HVDD
Analog
42
VDD
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PIN CONNECTIONS
Table 1. Pin Definitions (continued) A functional description of each pin can be found in the Functional Pin Description section beginning on page 21.
Die Analog - Pin 43 EP Pin Name VSS Exposed Pad Formal Name Voltage Regulator Ground Exposed Pad Definition Ground pin for the connection of all non-power ground connections (microcontroller and sensors). The exposed pad pin on the bottom side of the package conducts heat from the chip to the PCB board.
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ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding limits on any pin may cause permanent damage to the device.
Rating ELECTRICAL RATINGS Supply Voltage Analog Chip Supply Voltage under Normal Operation (Steady-state) Analog Chip Supply Voltage under Transient Conditions(1) MCU Chip Supply Voltage Input Pin Voltage Analog Chip Microcontroller Chip Maximum Microcontroller Current per Pin All Pins except VDD, VSS, PTA0:PTA4 PTA0:PTA4 Maximum Microcontroller VSS Output Current Maximum Microcontroller VDD Input Current LIN Supply Voltage Normal Operation (Steady-state) Transient Input Voltage (per ISO7637 Specification) and with External Components (Figure 4, page 18) ESD Voltage(2) Human Body Model H0 pin Human Body Model all other pins Machine Model Charge Device Model VESD1-1 VESD1-2 VESD2 VESD3 1000 2000 200 750 VBUS(SS) VBUS(PK) -18 to 40 -150 to 100 V IPIN(1) IPIN(2) IMVSS IMVDD 15 25 100 100 mA mA V VIN(ANALOG) VIN(MCU) -0.3 to 5.5 VSS -0.3 to VDD +0.3 mA VSUP(SS) VSUP(PK) VDD -0.3 to 28 -0.3 to 40 -0.3 to 5.5 V V Symbol Value Unit
Notes 1. Transient capability for pulses with a time of t < 0.5 sec. 2. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100pF, RZAP = 1500), the Machine Model (CZAP =200pF, RZAP = 0) and the Charge Device Model, Robotic (CZAP = 4.0pF).
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ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS
Table 2. Maximum Ratings (continued) All voltages are with respect to ground unless otherwise noted. Exceeding limits on any pin may cause permanent damage to the device.
Rating THERMAL RATINGS Operating Ambient Temperature(3) Operating Junction Temperature(4) Storage Temperature Peak Package Reflow Temperature During Reflow(6), (7) TA TJ TSTG TPPRT -40 to 85 -40 to 125 -40 to 150 Note 7 C C C C Symbol Value Unit
Notes 3. The limiting factor is junction temperature; taking into account the power dissipation, thermal resistance, and heat sinking. 4. The temperature of analog and MCU die is strongly linked via the package, but can differ in dynamic load conditions, usually because of higher power dissipation on the analog die. The analog die temperature must not exceed 150C under these conditions. 5. Pin soldering temperature is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. 6. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. 7. Freescale's Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0V VSUP 16V, -40C TJ 125C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions, unless otherwise noted.
Characteristic SUPPLY VOLTAGE RANGE Nominal Operating Voltage Extended Operating Voltage (LIN only SUPPLY CURRENT RANGE Normal Mode(9) VSUP = 12V, Analog Chip in Normal Mode (PSON=1), MCU Operating Using Internal Oscillator at 32MHz (8.0MHz Bus Frequency), SPI, ESCI, ADC Enabled Stop Mode(9), (10) VSUP = 12V, Voltage Regulator with limited current capability Sleep Mode(9), (10) VSUP = 12V, Voltage Regulator off DIGITAL INTERFACE RATINGS (ANALOG DIE) Output pins RST_A, IRQ_A, RXD (MISO probe only) Low-state Output Voltage (IOUT = -1.5mA) High-state Output Voltage (IOUT = 250A) Output pin RXD - Capacitance(11) Input pins RST_A, PWM (SS, MOSI, TXD probe only) Input Logic Low Voltage Input Logic High Voltage Input pins - Capacitance(11) Pins IRQ_A, RST_A - Pullup Resistor Pins SS - Pullup Resistor Pins MOSI, SPSCK, PWM - Pulldown Resistor Pin TXD - Pullup Current Source VIL VIH CIN RPULLUP1 RPULLUP2 RPULLDOWN IPULLUP - 3.5 - - - - - - - 4.0 10 100 100 35 1.5 - - - - - - pF k k k A VOL VOH COUT - 3.85 - - - 4.0 0.4 - - pF V V ISLEEP -- 12 20 A IRUN -- 25 -- mA 8..18V)(9) VSUP1 VSUP2 9.0 7.5 -- -- 16 20 V V Symbol Min Typ Max Unit
ISTOP
--
40
50
A
Notes 8. Device is fully functional, but some of the parameters might be out of spec. 9. Total current measured at GND pins. 10. Stop and Sleep mode current will increase if VSUP exceeds 15V. 11. This parameter is guaranteed by process monitoring but is not production tested.
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued) All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0V VSUP 16V, -40C TJ 125C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions, unless otherwise noted.
Characteristic SYSTEM RESETS AND INTERRUPTS Low Voltage Reset (LVR) Threshold Hysteresis Low Voltage Interrupt (LVI) Threshold Hysteresis High Voltage Interrupt (HVI) Threshold Hysteresis High Temperature Interrupt (HTI)(12) Threshold TJ Hysteresis High Temperature Reset (HTR)(12) Threshold TJ Hysteresis VOLTAGE REGULATOR(13) Normal Mode Output Voltage(14) IOUT = 60mA, 7.5V < VSUP < 20V IOUT = 60mA, VSUP < 7.5V and VSUP > 20V Normal Mode Total Output Current Load Regulation - IOUT = 60mA, VSUP = 9.0V, TJ = 125C STOP Mode Output Voltage(14) STOP Mode Total Output Current VDDRUN1 VDDRUN2 IOUTRUN VLR VDDSTOP IOUTSTOP 4.75 4.75 - - 4.75 150 5.0 5.0 120 - 5.0 500 5.25 5.25 150 100 5.25 1100 mA mV V A V TRON TIH 155 5.0 - - 180 10.0 TION TIH 125 5.0 - - 150 10.0 C VHVION VHVI_HYS 20 0.5 - - 24 1.5 C VLVION VLVI_HYS 6.0 0.3 - - 7.5 0.8 V VLVRON VLVR_HYS 3.8 50 4.2 - 4.65 300 V mV V Symbol Min Typ Max Unit
Notes 12. This parameter is guaranteed by process monitoring but is not production tested. 13. Specification with external low ESR ceramic capacitor 1.0F< C < 4.7F and 200m ESR 10. Its not recommended to use capacitor values above 4.7F 14. When switching from Normal to Stop mode or from Stop mode to Normal mode, the output voltage can vary within the output voltage specification.
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued) All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0V VSUP 16V, -40C TJ 125C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions, unless otherwise noted.
Characteristic LIN PHYSICAL LAYER LIN Transceiver Output Voltage Recessive State, TXD HIGH, IOUT = 1.0A Dominant State, TXD LOW, 500 External Pullup Resistor Normal Mode Pullup Resistor to VSUP Stop, Sleep Mode Pullup Current Source Output Current Shutdown Threshold Output Current Shutdown Timing Leakage Current to GND VSUP Disconnected, VBUS at 18V Recessive state, 8.0V VSUP 18V, 8.0V VBUS 18V, VBUS VSUP GND Disconnected, VGND = VSUP, VBUS at -18V LIN Receiver Receiver Threshold Dominant Receiver Threshold Recessive Receiver Threshold Center Receiver Threshold Hysteresis VBUS_DOM VBUS_REC VBUS_CNT VBUS_HYS - 0.6 0.475 - - - 0.5 - 0.4 - 0.525 0.175 IBUS IBUS-PAS-REC IBUS-NOGND - 0.0 -1.0 1.0 3.0 - 10 20 1.0 A A mA VSUP V LIN_REC V LIN_DOM R PU IPU IBLIM IBLS VSUP -1 -- 20 -- 100 5.0 -- -- 30 20 230 - -- 1.4 47 -- 280 40 k A mA s V Symbol Min Typ Max Unit
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued) All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0V VSUP 16V, -40C TJ 125C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions, unless otherwise noted.
Characteristic HIGH SIDE OUTPUT HS1 Switch On Resistance TJ = 25C, ILOAD = 1.0A Over-current Shutdown Over-current Shutdown blanking Current to Voltage Ratio(16) time(15) RDS(ON)-HS1 IHSOC1 tOCB CRRATIOHS1 - 6.0 - 0.84 185 - 4-8 1.2 225 9.0 - 1.56 A s V/A m Symbol Min Typ Max Unit
VADOUT [V] / IHS [A], (measured and trimmed IHS = 2.0A) High Side Switching Frequency(15) High Side Freewheeling Diode Forward Voltage TJ = 25C, ILOAD = 1.0A Leakage Current HIGH SIDE OUTPUTS HS2 AND HS3(17) Switch On Resistance TJ = 25C, ILOAD = 1.0 A Over-current Shutdown Over-current Shutdown blanking time(15) Current to Voltage Ratio(16) RDS(ON)-HS23 IHSOC23 tOCB CRRATIOHS23 - 3.6 - 1.16 440 - 4-8 1.66 500 5.6 - 2.16 A s V/A m ILeakHS - <0.2 10 A fPWMHS VHSF - - - 0.9 25 - kHz V
VADOUT [V] / IHS [A], (measured and trimmed IHS = 2.0A) High Side Switching Frequency(15) High Side Freewheeling Diode Forward Voltage TJ = 25C, ILOAD = 1.0A Leakage Current ILeakHS - <0.2 10 A fPWMHS VHSF - - - 0.9 25 - kHz V
Notes 15. This parameter is guaranteed by process monitoring but is not production tested. 16. This parameter is guaranteed only if correct trimming was applied. 17. The high side HS3 can be only used for resistive loads.
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued) All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0V VSUP 16V, -40C TJ 125C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions, unless otherwise noted.
Characteristic HALF-BRIDGE OUTPUTS HB1 AND HB2 Switch On Resistance High Side, TJ = 25C, ILOAD = 1.0A Low Side, TJ = 25C, ILOAD = 1.0A Over-current Shutdown High Side Low Side Over-current Shutdown blanking time(18) Switching Frequency(18) Freewheeling Diode Forward Voltage High Side, TJ = 25C, ILOAD = 1.0A Low Side, TJ = 25C, ILOAD = 1.0A Leakage Current Low Side Current to Voltage Ratio(19) VADOUT [V] / IHB [A], CSA = 1, (measured and trimmed IHB = 200mA) VADOUT [V] / IHB [A], CSA = 0, (measured and trimmed IHB = 500mA) HALF-BRIDGE OUTPUTS HB3 AND HB4 Switch On Resistance High Side, TJ = 25C, ILOAD = 1.0A Low Side, TJ = 25C, ILOAD = 1.0A Over-current Shutdown High Side Low Side Over-current Shutdown blanking time(18) Switching Frequency(18) Freewheeling Diode Forward Voltage High Side, TJ = 25C, ILOAD = 1.0A Low Side, TJ = 25C, ILOAD = 1.0A Leakage Current Low Side Current to Voltage Ratio(19) VADOUT [V] / IHB [A], CSA = 1, (measured and trimmed IHB = 500mA) VADOUT [V] / IHB [A], CSA = 0, (measured and trimmed IHB = 2.0A) Notes 18. This parameter is guaranteed by process monitoring but is not production tested. 19. This parameter is guaranteed only if correct trimming was applied VHSF VLSF ILeakHB CRRATIOHB34 3.5 0.7 5.0 1.0 6.5 1.3 - - - 0.9 0.9 <0.2 - - 10 A V/A tOCB fPWM IHBOC34 4.8 4.8 - - - - 4-8 - 7.2 7.2 - 25 s kHz V RDS(ON)-HB34 - - 275 275 325 325 A m VHSF VLSF ILeakHB CRRATIOHB12 17.5 3.5 25.0 5.0 32.5 6.5 - - - 0.9 0.9 <0.2 - - 10 A V/A tOCB fPWM IHBOC12 1.0 1.0 - - - - 4-8 - 1.5 1.5 - 25 s kHz V RDS(ON)-HB12 - - 750 750 900 900 A m Symbol Min Typ Max Unit
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued) All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0V VSUP 16V, -40C TJ 125C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions, unless otherwise noted.
Characteristic SWITCHABLE VDD OUTPUT HVDD Over-current Shutdown Over-current Shutdown Blanking Time(20) HVDDT1:0 = 00 HVDDT1:0 = 01 HVDDT1:0 = 10 HVDDT1:0 = 11 Over-current Flag Delay(20) Dropout Voltage @ ILOAD = 20mA VSUP DOWN SCALER(21) Voltage Ratio (RATIO VSUP = VSUP / VADOUT) INTERNAL DIE TEMPERATURE SENSOR(21) Voltage / Temperature Slope(20) Output Voltage @25C STtoV VT25 - 1.7 26 1.9 - 2.1 mV/C V RATIOVSUP 4.75 5.0 5.25 - tHVDDOCFD VHVDDDROP IHVDDOC tHVDDOCB - - - - - - 950 536 234 78 0.5 110 - - - - - 300 ms mV 25 35 50 mA s Symbol Min Typ Max Unit
Notes 20. This parameter is guaranteed by process monitoring but is not production tested. 21. This parameter is guaranteed only if correct trimming was applied
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued) All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0V VSUP 16V, -40C TJ 125C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions, unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
HALL-EFFECT SENSOR INPUT H0 - GENERAL PURPOSE INPUT MODE (H0MS = 0) Input Voltage Low Threshold Input Voltage High Threshold Input Voltage Hysteresis Pullup resistor VLT VHT VHH RPH - 3.5 100 7.0 - - - 10 1.5 - 500 13 V V mV k
HALL-EFFECT SENSOR INPUT H0 - 2PIN HALL SENSOR INPUT MODE (H0MS = 1) Output Voltage VSUP < 17V VSUP >17V Output Drop @ IOUT = 15mA Sense Current Threshold Sense Current Hysteresis Sense Current Limitation ANALOG INPUT A0, A0CST Current Source A0, A0CST(22), (23) CSSEL1:0 = 00 CSSEL1:0 = 01 CSSEL1:0 = 10 CSSEL1:0 = 11 WAKE-UP INPUT L0 Input Voltage Threshold Low Input Voltage Threshold High Input Voltage Hysteresis Input Current Wake-up Filter Time(24) VLT VHT VLH IN tWUP - 3.5 0.5 -10 - - - - - 20 1.5 - - 10 - V V V A s ICS1 ICS2 ICS3 ICS4 - - - - 40 120 320 800 - - - - A VHALL1 VHALL2 VH0D IHSCT IHSCH VHSCLIM - - - 6.0 650 20 VSUP-1.2 - - 7.9 - 40 - 15.8 2.5 10 1650 70 V mA A mA V
Notes 22. This parameter is guaranteed only if correct trimming was applied 23. The current values are optimized to read a NTC temperature sensor, e.g. EPCOS type B57861 (R25 = 3000, R/T characteristic 8016) 24. This parameter is guaranteed by process monitoring but is not production tested.
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ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics All characteristics are for the analog chip only. Please refer to the 68HC908EY16 datasheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0V VSUP 16V, -40C TJ 125C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions, unless otherwise noted.
Characteristic LIN PHYSICAL LAYER Driver Characteristics for Normal Slew Rate(25), (26) Dominant Propagation Delay TXD to LIN Dominant Propagation Delay TXD to LIN Recessive Propagation Delay TXD to LIN Recessive Propagation Delay TXD to LIN Duty Cycle 1: D1 = tBUS_REC(MIN) / (2 x tBIT), tBIT = 50s, VSUP = 7.0V..18V Duty Cycle 2: D2 = tBUS_REC(MAX) / (2 x tBIT), tBIT = 50s, VSUP = 7.6V..18V Driver Characteristics for Slow Slew Rate(25), (27) Dominant Propagation Delay TXD to LIN Dominant Propagation Delay TXD to LIN Recessive Propagation Delay TXD to LIN Recessive Propagation Delay TXD to LIN Duty Cycle 3: D3 = tBUS_REC(MIN) / (2 x tBIT), tBIT = 96s, VSUP = 7.0V..18V Duty Cycle4: D4 = tBUS_REC(MAX) / (2 x tBIT), tBIT = 96s, VSUP = 7.6V..18V Driver Characteristics for Fast Slew Rate LIN High Slew Rate (Programming Mode) Receiver Characteristics and Wake-up Timings Receiver Dominant Propagation Delay(28) Receiver Recessive Propagation Delay(28) Receiver Propagation Delay Symmetry Bus Wake-up Deglitcher Bus Wake-up Event Reported
(29)
Symbol
Min
Typ
Max
Unit
t DOM-MIN t DOM-MAX t REC-MIN t REC-MAX D1 D2
-- -- -- -- 0.396 -
-- -- -- -- - -
50 50 50 50 - 0.581
s s s s
t DOM-MIN t DOM-MAX t REC-MIN t REC-MAX D3 D4
-- -- -- -- 0.417 -
-- -- -- -- - -
100 100 100 100 - 0.590
s s s s
SRFAST
--
20
--
V/s
t RL t RH t R-SYM t PROPWL t WAKE
-- -- -2.0 30 --
3.5 3.5 -- 50 20
6.0 6.0 2.0 150 --
s s s s s
Notes 25. VSUP from 7.0V to 18V, bus load R0 and C0 1.0nF/1.0k, 6.8nF/660, 10nF/500. Measurement thresholds: 50% of TXD signal to LIN signal threshold defined at each parameter. 26. See Figure 6, page 18. 27. See Figure 7, page 19. 28. Measured between LIN signal threshold VIL or VIH and 50% of RXD signal. 29. t WAKE is typically 2 internal clock cycles after LIN rising edge detected. See Figure 9 and Figure 8, page 19. In Sleep mode the VDD rise time is strongly dependent upon the decoupling capacitor at VDD pin.
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ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics (continued) All characteristics are for the analog chip only. Please refer to the 68HC908EY16 datasheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0V VSUP 16V, -40C TJ 125C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions, unless otherwise noted.
Characteristic SPI INTERFACE TIMING SPI Operating Recommended Frequency(30) f SPIOP 0.25 -- 4.0 MHz Symbol Min Typ Max Unit
State Machine
Reset Low Level Duration after VDD High Normal Request Timeout tRST tNORMREQ 0.8 51 1.25 80 1.94 150 ms ms
Window Watchdog Timer(31)
Watchdog Period (WDP1:0 = 00) Watchdog Period (WDP1:0 = 01) Watchdog Period (WDP1:0 = 10) Watchdog Period (WDP1:0 = 11) tWD80 tWD40 tWD20 tWD10 52 26 13 6.5 80 40 20 10 124 62 31 15.5 ms ms ms ms
Notes 30. This parameter is guaranteed by process monitoring but is not production tested. 31. This parameter is guaranteed only if correct trimming was applied. Additionally See Watchdog Period Range Value (AWD Trim) on page 50
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MICROCONTROLLER PARAMETRICS DYNAMIC ELECTRICAL CHARACTERISTICS
MICROCONTROLLER PARAMETRICS
Table 5. Microcontroller For a detailed microcontroller description, refer to the MC68HC908EY16 datasheet.
Module Core Timer Flash RAM ADC SPI ESCI Description High Performance HC08 Core with a Maximum Internal Bus Frequency of 8.0MHz Two 16-Bit Timers with 2 Channels (TIM A and TIM B) 16K Bytes 512 Bytes 10-Bit Analog-to-Digital Converter SPI Module Standard Serial Communication Interface (SCI) Module Bit-Time Measurement Arbitration Prescaler with Fine Baud Rate Adjustment Internal Clock Generation Module
ICG
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TIMING DIAGRAMS DYNAMIC ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
LIN, L0
Transient Pulse Generator
10k
1nF
Note: Waveform in accordance to ISO7637 part 1, test pulses 1, 2, 3a and 3b.
Figure 4. Test Circuit for Transient Test Pulses
VSUP VSUP
TXD LIN RXD
R0
R0R0 and C0 combinations: and C0 Combinations: * 1.0k and 1.0nF - 1k Ohm and 1nF * 600 and 6.8nF6.8nF - 660 Ohm and * 500 and 10nF 10nF - 500 Ohm and
C0
Figure 5. Test Circuit for LIN Timing Measurements
TXD
VLIN
tREC-MAX tDOM-MIN 58.1% VSUP 74.4% VSUP 60% VSUP 42.2% VSUP
LIN
40% VSUP 28.4% VSUP tDOM-MAX tREC-MIN
RXD
tRL
tRH
Figure 6. LIN Timing Measurements for Normal Slew Rate
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TIMING DIAGRAMS DYNAMIC ELECTRICAL CHARACTERISTICS
TXD
VLIN
tREC-MAX tDOM-MIN 61.6% VSUP 77.8% VSUP 60% VSUP 38.9% VSUP
LIN
40% VSUP 25.1% VSUP tDOM-MAX tREC-MIN
RXD
tRL
tRH
Figure 7. LIN Timing Measurements for Slow Slew Rate
VLIN_REC Vrec
LIN
0.4VSUP 0.4 VSUP
Dominant level Dominant Level
IRQ_A
tTpropWL PROPWL
tTwake WAKE
Figure 8. Wake-up Stop Mode Timing
Vrec VLIN_REC
LIN
0.4VSUP 0.4 V
SUP
Dominantlevel Dominant Level
VDD
tTpropWL PROPWL
tTwake WAKE
Figure 9. Wake-up Sleep Mode Timing
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TIMING DIAGRAMS DYNAMIC ELECTRICAL CHARACTERISTICS
VSUP
VDD
RST_A
TRST TNORMREQ
Figure 10. Power On Reset and Normal Request Timeout Timing
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FUNCTIONAL DESCRIPTION INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 908E621 was designed and developed as a highly integrated and cost-effective solution for automotive and industrial applications. For automotive body electronics, the 908E621 is well suited to perform complete mirror control via a three wire LIN bus. This device combines an HC908EY16 MCU core with flash memory together with a SMARTMOS IC chip. The SMARTMOS IC chip combines power and control in one chip. Power switches are provided on the SMARTMOS IC configured as half-bridge outputs and three high side switches. Other ports are also provided, which include one Hall-effect sensor input port, one analog input port with a switched current source, one wake-up pin, and a selectable HVDD pin. An internal voltage regulator provides power to the MCU chip. Also included in this device is a LIN physical layer, which communicates using a single wire. This enables this device to be compatible with three wire bus systems, where one wire is used for communication, one for battery, and one for ground.
FUNCTIONAL PIN DESCRIPTION
See Figure 2, 908E621 Simplified Internal Block Diagram, page 2, for a graphic representation of the various pins referred to in the following paragraphs. Also, see the pin diagram on page 3 for a depiction of the pin locations on the package. PTC0/MISO and PTC1/MOSI are not accessible in this device and are internally connected to the MISO and MOSI SPI pins of the analog die. For details refer to the 68HC908EY16 datasheet.
PORT A I/O PINS
These pins are special function, bidirectional I/O port pins that are shared with other functional modules in the MCU. PTA0:PTA4 are shared with the keyboard interrupt pins, KBD0:KBD4. The PTA5/SPSCK pin is not accessible in this device and is internally connected to the SPI clock pin of the analog die. The PTA6/SS pin is not accessible in this device and is internally connected to the SPI slave select input of the analog die. For details refer to the 68HC908EY16 datasheet.
PORT D I/O PINS
PTD0/TACH0/BEMF and PTD1/TACH1 are special function, bidirectional I/O port pins that can also be programmed to be timer pins. PTD0/TACH0 pin is internally connected to the PWM input of the analog die and only accessible for test purposes (can not be used in the application). For details refer to the 68HC908EY16 datasheet.
PORT E I/O PIN
PTE0/TXD and PTE1/RXD are special function, bidirectional I/O port pins that can also be programmed to be enhanced serial communication. PTE0/TXD is internally connected to the TXD pin of the analog die. The connection for the receiver must be done externally. PTE1/RXD is internally connected to the RXD pin of the analog die and only accessible for test purposes (can not be used in the application). For details refer to the 68HC908EY16 datasheet.
PORT B I/O PINS
These pins are special function, bidirectional I/O port pins that are shared with other functional modules in the MCU. All pins are shared with the ADC module. PTB0/AD0 is internally connected to the ADOUT pin of the analog die, allowing diagnostic measurements to be calculated (e.g., current recopy, VSUP, etc.). The PTB1/AD1, PTB2/AD2, PTB6/AD6/TBCH0, PTB7/ AD7/TBCH1 pins are not accessible in this device. For details refer to the 68HC908EY16 datasheet.
EXTERNAL INTERRUPT PIN (IRQ)
The IRQ pin is an asynchronous external interrupt pin. This pin contains an internal pullup resistor that is always activated, even when the IRQ pin is pulled LOW. For details refer to the 68HC908EY16 datasheet.
PORT C I/O PINS
These pins are special function, bidirectional I/O port pins that are shared with other functional modules in the MCU. For example, PTC2:PTC4 are shared with the ICG module.
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FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION
EXTERNAL RESET PIN (RST)
A logic [0] on the RST pin forces the MCU to a known startup state. RST is bidirectional, allowing a reset of the entire system. It is driven LOW when any internal reset source is asserted. This pin contains an internal pullup resistor that is always activated, even when the reset pin is pulled LOW. For details refer to the 68HC908EY16 datasheet.
HALL-EFFECT SENSOR INPUT PIN (H0)
The Hall-effect sensor input pin H0 provides an input for Hall-effect sensors (2pin or 3pin) or a switch.
ANALOG INPUT PINS (A0, A0CST)
These pins are analog inputs with selectable current source values. The A0CST intent is to trim the A0 input.
WAKE-UP INPUT PIN (L0) POWER SUPPLY PINS (VSUP1:VSUP8)
VSUP1:VSUP8 are device power supply pins. The nominal input voltage is designed for operation from 12V systems. Owing to the low ON-resistance and current requirements of the half-bridge driver outputs and high side output drivers, multiple VSUP pins are provided. All VSUP pins must be connected to get full chip functionality. This pin is 40V rated input. It can be used as wake-up source for a system wake-up. The input is falling or rising edge sensitive. Important: If unused this pin should be connected to VSUP or GND to avoid parasitic transitions. In Low Power mode this could lead to random wake-up events.
SWITCHABLE VDD OUTPUT PIN (HVDD)
The HVDD pin is a switchable VDD output for driving resistive loads requiring a regulated 5.0V supply (e.g., 3-pin Hall-effect sensors or potentiometers). The output is shortcircuit protected.
POWER GROUND PINS (GND1:GND4)
GND1:GND4 are device power ground connections. Owing to the low ON-resistance and current requirements of the half-bridge driver outputs and high side output drivers, multiple pins are provided. GND1 and GND2 pins must be connected to get full chip functionality.
LIN BUS PIN (LIN)
The LIN pin represents the single wire bus transmitter and receiver. It is suited for automotive bus systems and is based on the LIN bus specification.
HALF-BRIDGE OUTPUT PINS (HB1:HB4)
The 908E621 device includes power MOSFETs configured as four half-bridge driver outputs. The HB3:HB4 have a lower RDS(ON), to run higher currents (e.g. fold motor), than the HB1:B2 outputs. The HB1:HB4 outputs are short-circuit and overtemperature protected, and they feature current recopy. Over-current protection is done on both high side and low side FET's. The current recopy are done on the low side MOSFETs.
+5.0V VOLTAGE REGULATOR OUTPUT PIN (VDD)
The VDD pin is needed to place an external capacitor to stabilize the regulated output voltage. The VDD pin is intended to supply the embedded microcontroller. Important: The VDD pin should not be used to supply other loads; use the HVDD pin for this purpose. The VDD, EVDD and VDDA/VREFH pins must be connected together.
VOLTAGE REGULATOR GROUND PIN (VSS)
The VSS pin is the ground pin for the connection of all nonpower ground connections (microcontroller and sensors). Important: VSS, EVSS and VSSA/VREFL pins must be connected together.
HIGH SIDE OUTPUT PINS (HS1:HS3)
The HS output pins are a low RDS(ON) high side switches. Each HS switch is protected against over-temperature and over-current. The output is capable of limiting the inrush current with an automatic PWM or feature a real PWM capability using the PWM input. The HS1 has a lower RDS(ON), to run higher currents (e.g. heater), than the HS2 and HS3 outputs. For the HS1 two pins (HS1a:HS1b) are necessary for the current capability and have to be connected externally. Important: The HS3 can be only used to drive resistive loads.
RESET PIN (RST_A)
RST_A is the bidirectional reset pin of the analog die. It is an open drain with pullup resistor and must be connected to the RST pin of the MCU.
INTERRUPT PIN (IRQ_A)
IRQ_A is the interrupt output pin of the analog die indicating errors or wake-up events. It is an open drain with pullup resistor and must be connected to the IRQ pin of the MCU.
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FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION
ADC SUPPLY/REFERENCE PINS (VDDA/VREFH AND VSSA/VREFL)
VDDA and VSSA are the power supply pins for the analogto-digital converter (ADC). VREFH and VREFL are the reference voltage pins for the ADC. The supply and reference signals are internally connected. It is recommended that a high quality ceramic decoupling capacitor be placed between these pins. For details refer to the 68HC908EY16 datasheet.
TEST MODE PIN (TESTMODE)
This pin is for test purpose only. In the application this pin has to be forced to GND. For Programming/Test this pin has to be forced to VDD to bring the analog die into Test mode. In Test mode the Reset Timeout (80ms) is disabled and the LIN receiver is disabled NOTE: After detecting a RESET (internal or external), the PSON bit needs to be set within 80ms. If not, the device will automatically enter sleep mode.
MCU TEST PIN (FLSVPP)
This pin is for test purposes only. This pin should either be left open (not connected) or can be connected to GND.
MCU POWER SUPPLY PINS (EVDD AND EVSS)
EVDD and EVSS are the power supply and ground pins. The MCU operates from a single power supply. Fast signal transitions on MCU pins place high, shortduration current demands on the power supply. To prevent noise problems, take special care to provide power supply bypassing at the MCU. For details refer to the 68HC908EY16 datasheet.
VDDA/VREFH EVDD 0,1F 4,7F VDD
NO CONNECT PINS (NC)
The NC pins are not connected internally. Note: Each of the NC pins can be left open or connected to ground (recommended).
EXPOSED PAD PIN
The exposed pad pin on the bottom side of the package conducts heat from the chip to the PCB board. For thermal performance, the pad must be soldered to the PCB board. It is recommended that the pad be connected to the ground potential.
C
Analog Die
VSS
EVSS VSSA/VREFL
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FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
MM908E621 - Functional Block Diagram SMARTMOS Analog Control IC Internal Regulators & Safety Voltage Regulation Switched VDD Reset, IRQ & Wake-up Watchdog Timer Power Module w/Power-On Reset Internal Clock Module 10-Bit ADC Module I/O Ports A, B, C, D, E Analog Input w/Integrated Current Source Outputs High Side Drivers & Diagnostics H-Bridge Drivers & Diagnostics
Internal Regulators & Safety
SMARTMOS ANALOG CONTROL IC INTERNAL REGULATORS & SAFETY: VOLTAGE REGULATION
The voltage regulator circuitry provides the regulated voltage for the Analog IC as well as the VDD/VSS rails for the core IC. The on-chip regulator consists of two elements, the main regulator, and the low voltage reset circuit. The VDD regulator accepts an unregulated input supply, and provides a regulated VDD supply to all digital sections of the device. The output of the regulator is also connected to the VDD pin, to provide the 5.0V to the microcontroller. watchdog reset event will reset all registers in the SPI, excluding the RSR.
MC68HC908EY16 Core M68HC08 CPU w/ ALU, RAM, Flash ROM
Control & Interface Hall Sensor Interface LIN Interface Analog Multiplexer SPI Interface & PWM Control
Timer Modules Communication Modules Reset & IRQ
Outputs MC68HC908EY16 Core
Control & Interface
RESET, IRQ & WAKE-UP
There are several functions on the Analog IC that can generate a reset or wake-up signal to the core IC. There is a pin that is used to detect an external wake-up event. The Reset signal has many possible sources in the Analog IC circuitry. The IRQ function on the Analog IC, will notify the core IC of pending system critical conditions.
CONTROL & INTERFACE: SWITCHED VDD
This function provides a switchable +5.0V VDD rail for an external load.
HALL SENSOR INTERFACE
This interface can be configured to support an input pin as a general purpose input, or as a hall-effect sensor input, to be able to read 3-pin / 2-pin hall sensors or switches.
WATCHDOG TIMER
The watchdog timer module generates a reset, in case of a watchdog timeout or wrong watchdog timer reset. A
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FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION
SPI INTERFACE & PWM CONTROL
The SPI and PWM interfaces are mastered by the core IC (CPU), and are used to control the output functions of the Analog IC, as well as to report status and failure information of the Analog IC.
MM68HC908EY16 CORE IC M68HC08 CPU W/ALU, RAM, FLASH ROM
This possesses the functionality of the CPU08 architecture, along with 512 bytes of RAM and 15,872 bytes of FLASH memory, with in-circuit programming.
LIN INTERFACE
The LIN interface function supports the single wire bus transmit and receive capabilities. It is suited for automotive bus systems and is based on the LIN bus/physical layer specification. The LIN driver is a low side MOSFET with slope control, internal current limitation, and thermal shutdown.
POWER MODULE W/P0WER-ON-RESET
This block of circuitry manages the power supplied to the core IC, as well as providing POR, LVI, Watchdog timer, and MCU supervision circuitry (COP).
ANALOG MULTIPLEXER
To be able to have different sources for the MCU with one single signal, an analog multiplexer is integrated in the analog IC. This multiplexer has eleven different sources on the Analog IC, which can be selected with the SS[3:0] bits (through SPI communication) in the A0MUCTL register.
INTERNAL CLOCK MODULE This module provides the clocks needed by the core IC functions, without the need for external components. Software selectable bus frequencies are available. It also provides a clock monitor function. 10-BIT ADC MODULE
ANALOG INPUT W/INTEGRATED CURRENT SOURCE
The terminal A0 provides a switchable current source, to allow the reading of switches, NTC, etc., without the need for an additional supply line for the sensor (single wire). There are four different selectable current source values.
This module provides an 8-channel, 10-bit successive approximation analog-to-digital converter (ADC).
I/O PORTS A, B, C, D, E
There are many I/O pins that are controlled by the CPU through the several I/O ports of the core IC.
OUTPUTS: HIGH SIDE DRIVERS & DIAGNOSTICS
The HS outputs are low RDS(ON) high side switches. Each HS switch is protected against over-temperature and over-current. The output is capable of limiting the inrush current with an automatic PWM, or feature a real PWM capability using the PWM input.
TIMER MODULES
There are two 16-bit, 2 channel timer interface modules with selectable input capture, output compare, and PWM capabilities, for each channel.
COMMUNICATION MODULES
There are several communication functions supported by the core IC, including an enhanced serial communication interface module (ESCI) for the LIN communication, and an SPI module for inter-IC communication.
H-BRIDGE DRIVERS & DIAGNOSTICS
The device includes power MOSFETs configured as four half-bridge driver outputs. These outputs are short-circuit and over-temperature protected. Over-current protection is done on both high side and low side MOSFETs.
RESET & IRQ
There are interrupt and reset connections between the Analog IC and the core IC, for concise control and error/ exception management.
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FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES 908E621 ANALOG DIE MODES OF OPERATION
The 908E621 offers three operating modes: Normal (Run), Stop, and Sleep. In Normal mode, the device is active and is operating under normal application conditions. The Stop and Sleep modes are low power modes with wake-up capabilities. The different modes can be selected by the STOP and SLEEP bits in the System Control Register. Figure 11 describes how transitions are done between the different operating modes and Table 6, page 28, gives an overview of the operating modes.
Power Down
Power Up
RESET
VDD High and Reset Delay (tRST) expired
Normal Request
TESTMODE = 1
VDD Low PSON = 1
PSON = 0 and Normal Request timeout (tNORMREQ) expired
Reset (LVR, HTR, WDR, ext. Reset)
NORMAL
SLEEP Command
Wake-Up (Reset) Reset (LVR, ext. Reset)
SLEEP
STOP
Reset (LVR, ext. Reset, (HTR))
Figure 11. Operating Modes and Transitions Normal Mode This Mode is the normal operating mode of the device, all functions and power stages are active and can be enabled/ disabled. The voltage regulator provides the +5V VDD to the MCU. After a reset (e.g. Power-On-Reset, Wake-up from Sleep), the MCU has to set the PSON bit in the System Control Register within 80ms typical (tNORMREQ). This is to ensure the MCU has started up and is operating correctly. If the PSON bit is not set within the required time frame, the device enters SLEEP mode to reduce power consumption (fail safe). This MCU monitoring can be disabled (e.g. for programming) by applying VDD on the TESTMODE pin. Stop Mode In Stop mode, the voltage regulator still supplies the MCU with VDD (limited current capability). To enter the Stop mode, the STOP bit in the System Control Register must be set, and the MCU has to be stopped also (see 908EY16 datasheet for details). Wake-up from this mode is possible by the LIN bus activity or the wake-up input L0. It is maskable with the LINIE and/or L0IE bits in the Interrupt Mask Register. The analog die is generating an interrupt on IRQ_A pin to wake-up the MCU. The wake-up / interrupt source can be evaluated with the L0IF and LINIF bits in the Interrupt Flag Register. Stop mode has a higher current consumption than Sleep mode, but allows a quicker wake-up. Additionally the wake-
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STOP Command
Wake-Up Interrupt
FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES
up sources can be selected (maskable), which is not possible in Sleep mode. Figure 12 show the procedure to enter the Stop mode and how the system is waking up.
MCU Power Die
From Reset
behaves like a power on reset. The wake-up / reset source can be evaluated by the L0WF and/or LINWF bits in the Reset Status Register. Sleep mode has a lower current consumption than Stop mode, but requires a longer time to wake-up. The wake-up sources can not be selected (not maskable). Figure 13 show the procedure to enter the Sleep mode and how a wake-up is performed.
MCU
initialize
Power Die
From Reset
operate
Enable/disable LIN/L0 wakeup
initialize
SPI: STOP =1
Switch to VREG low current mode
operate
MCU STOP
Wake-up on LIN or L0 ?
SPI: SLEEP =1
Switch off VREG VDD low, RST low
Assert IRQ IRQ interrupt ? Switch to VREG high current mode SPI: reason for interrupt
Wake-up on LIN or L0 ?
Store Wake-up Event
Figure 12. STOP Mode Wake-up Procedure Sleep Mode In Sleep mode, the voltage regulator is turned off and the MCU is not supplied (VDD = 0V), also the RST_A pin is pulled low. To enter the Sleep mode, the Sleep bit in the System Control Register has to be set. Wake-up from this mode is possible by LIN bus activity or the wake-up input L0, and is not maskable. The wake-up
Start VREG VDD high, RST high
Figure 13. SLEEP Mode Wake-up Procedure Table 6 summarized the Operating modes.
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FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES
Table 6. Operating Modes Overview
Device Mode Reset Voltage Regulator VDD ON Wake-up Capabilities N/A
RST_A
Output LOW
MCU monitoring/ Power Stages Watchdog Function Disabled tNORMREQ (80ms typical) time out to set PSON bit in System Control Register Window Watchdog active if enabled Disabled
LIN Interface Disabled
Normal Request
VDD ON
N/A
HIGH
Disabled
Disabled
Normal (Run)
VDD ON
N/A LIN wake-up, L0 state change (SPI PSON=1)(32) LIN wake-up L0 state change
HIGH
Enabled
Enabled
Stop
VDD ON with limited current capability
HIGH
Disabled
Disabled
Recessive state with wake-up capability Recessive state with wake-up capability
Sleep
VDD OFF
LOW
Disabled
Disabled
Notes 32. The SPI is still active in Stop mode. However, due to the limited current capability of the voltage regulator in Stop mode, the PSON bit has to be set before the increased current caused from a running MCU causes an LVR.
OPERATING MODES OF THE MCU
For a detailed description of the operating modes of the MCU, refer to the MC68HC908EY16 datasheet.
INTERRUPTS
The 908E621 has seven different interrupt sources. An interrupt pulse on the IRQ_A pin is generated to report an event or fault to the MCU. All interrupts are maskable and can be enabled/disabled via the SPI (Interrupt Mask Register). After reset, all interrupts are automatically disabled. Low Voltage Interrupt Low voltage interrupt (LVI) is related to external supply voltage VSUP. If this voltage falls below the LVI threshold, it will set the LVIF bit in the Interrupt Flag Register. If the low voltage interrupt is enabled (LVIE = 1), an interrupt will be initiated. During Sleep and Stop mode, the low voltage interrupt circuitry is disabled. High Voltage Interrupt The High voltage Interrupt (HVI) is related to the external supply voltage VSUP. If this voltage rises above the HVI threshold, it will set the HVIF bit in the Interrupt Flag Register. If the High voltage Interrupt is enabled (HVIE = 1), an interrupt will be initiated. During Stop and Sleep mode, the HVI circuitry is disabled. High Temperature Interrupt The high temperature interrupt (HTI) is generated by the on chip temperature sensors. If the chip temperature is above the HTI threshold, the HTIF bit in the Interrupt Flag Register
908E621
will be set. If the high temperature interrupt is enabled (HTIE = 1), an interrupt will be initiated. During Stop and Sleep mode, the HTI circuitry is disabled. LIN Interrupt The LIN Interrupt is related to the Stop mode. If the LIN interrupt is enabled (LINIE = 1) in Stop mode, an interrupt is asserted if a rising edge is detected, and the bus was dominant longer than TPROPWL. After the wake-up / interrupt, the LINIF indicates the reason for the wake-up / interrupt. Power Stage Fail Interrupt The power stage fail flag indicates an error condition on any of the power stages (see Figure 14, page 29). If the power stage fail interrupt is enabled (PSFIE = 1), an interrupt will be initiated if: During Stop and Sleep mode, the PSFI circuitry is disabled. HO Input Interrupt The H0 interrupt flag H0IF is set in run mode by a state change of the H0F flag (rising or falling edge on the enabled input). The interrupt function is available if the input is selected as General Purpose, or as a 2pin Hallsensor input. The interrupt is maskable with the H0IE bit in the Interrupt Mask Register. During Stop and Sleep mode, the H0I circuitry is disabled.
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FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES
L0 input Interrupt The L0 interrupt flag L0IF is set in run mode by a state change of the L0F flag (rising or falling edge). The interrupt is maskable with the L0IE bit in the interrupt mask register.
0 = high temperature condition has not occurred LVIF - Low Voltage Flag Bit This read/write flag is set on low voltage condition. Clear LVIF by writing a logic [1] to LVIF. If the low voltage condition is still present while writing a logical one to LVIF, the writing has no effect. Therefore, a low voltage interrupt cannot be lost due to inadvertent clearing of LVIF. Reset clears the LVIF bit. Writing a logic [0] to LVIF has no effect. 1 = low voltage condition has occurred 0 = low voltage condition has not occurred HVIF - High Voltage Flag Bit This read/write flag is set on a high voltage condition. Clear HVIF by writing a logic [1] to HVIF. If the high voltage condition is still present while writing a logical one to HVIF, the writing has no effect. Therefore, a high voltage interrupt cannot be lost due to inadvertent clearing of HVIF. Reset clears the HVIF bit. Writing a logic [0] to HVIF has no effect. 1 = high voltage condition has occurred 0 = high voltage condition has not occurred PSFIF - Power Stage Fail Bit This read-only flag is set on a fail condition on one of the power outputs (HBx, HSx, HVDD, H0). Reset clears the PSFIF bit. Clear this flag by writing a logic [1] to the appropriate fail flag. 1 = power stage fail condition has occurred 0 = power stage fail condition has not occurred
INTERRUPT FLAG REGISTER (IFR)
Register Name and Address: IFR - $0A Bit7
Read L0IF Write Reset H0IF LINIF 0 HTIF LVIF HVIF
6
5
4
3
2
1
Bit0
PSFIF
0
0
0
0
0
0
0
0
L0IF - L0 Input Flag Bit This read/write flag is set on a falling or rising edge at the L0 input. Clear L0IF by writing a logic [1] to L0IF. Reset clears the L0IF bit. Writing a logic [0] to L0IF has no effect. 1 = rising or falling edge on L0 input detected 0 = no state change on L0 input detected H0IF - H0 Input Flag Bit This read/write flag is set on a falling or rising edge at the H0 input. Clear H0IF by writing a logic [1] to H0IF. Reset clears the H0IF bit. Writing a logic [0] to H0IF has no effect. 1 = state change on the hallflags detected 0 = no state change on the hallflags detected LINIF - LIN Flag Bit This read/write flag is set if a rising edge is detected and the bus was dominant longer than TpropWL. Clear LINIF by writing a logic [1] to LINIF. Reset clears the LINIF bit. Writing a logic [0] to LINIF has no effect. 1 = LIN bus interrupt has occurred 0 = not LIN bus interrupt occurred since last clear HTIF - High Temperature Flag Bit This read/write flag is set on high temperature condition. Clear HTIF by writing a logic [1] to HTIF. If high temperature condition is still present while writing a logical one to HTIF, the writing has no effect. Therefore, a high temperature interrupt cannot be lost due to inadvertent clearing of HTIF. Reset clears the HTIF bit. Writing a logic [0] to HTIF has no effect. 1 = high temperature condition has occurred
H0OCF
H0OCF
HVDDOCF
HVDDOCF HB1OC HB2OC HB3OC HB4OC HS1OC
HSFF HBFF
PSFIF
HS2OC HS3OC
Figure 14. Principal Implementation of the PSFIF
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INTERRUPT MASK REGISTER (IMR)
Note: Disabling of the high temperature reset can lead to a destruction of the part in cases of high temperature. This bit was foreseen for test purposes only! HTIE - High Temperature Interrupt Enable Bit
2 1
HVIE
Register Name and Address: IMR - $09 Bit7
Read L0IE Write Reset H0IE LINIE HTRD HTIE LVIE PSFIE
6
5
4
3
Bit0
This read/write bit enables CPU interrupts by the high temperature flag, HTIF. Reset clears the HTIE bit. 1 = interrupt requests from HTIF flag enabled 0 = interrupt requests from HTIF flag disabled LVIE - Low Voltage Interrupt Enable Bit
0
0
0
0
0
0
0
0
L0IE - L0 Input Interrupt Enable Bit This read/write bit enables CPU interrupts by the L0 flag, L0IF. Reset clears the L0IE bit. 1 = interrupt requests from L0IF flag enabled 0 = interrupt requests from L0IF flag disabled H0IE - H0 Input Interrupt Enable Bit This read/write bit enables CPU interrupts by the Hallport flag, H0IF. Reset clears the H0IE bit. 1 = interrupt requests from H0IF flag enabled 0 = interrupt requests from H0IF flag disabled LINIE - LIN line Interrupt Enable Bit This read/write bit enables CPU interrupts by the LIN flag, LINIF. Reset clears the LINIE bit. 1 = interrupt requests from LINIF flag enabled 0 = interrupt requests from LINIF flag disabled HTRD - High Temperature Reset Disable Bit This read/write bit disables the high temperature reset function. Reset clears the HTRD bit. 1 = high temperature reset is disabled 0 = high temperature reset is enabled
This read/write bit enables CPU interrupts by the low voltage flag, LVIF.Reset clears the LVIE bit. 1 = interrupt requests from LVIF flag enabled 0 = interrupt requests from LVIF flag disabled HVIE - High Voltage Interrupt Enable Bit This read/write bit enables CPU interrupts by the high voltage flag, HVIF.Reset clears the HVIE bit. 1 = interrupt requests from HVIF flag enabled 0 = interrupt requests from HVIF flag disabled PSFIE - Power Stage Fail Interrupt Enable Bit This read/write bit enables CPU interrupts by power stage fail flag, PSFIF. Reset clears the PSFIE bit. 1 = interrupt requests from PSFIF flag enabled 0 = interrupt requests from PSFIF flag disabled
RESETS
The 908E621 has four internal and one external reset source. Each internal reset event will cause a reset pin low for tRST (1.25ms typical), after the reset event is gone.
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SPI REGISTERS
WDRE WD Reset Sensor
VDD
Reset SPI Register (not RSR) HTRD
HTR Reset Sensor
RST_A
Clear RSR and set POR Bit
RSR
MONO FLOP
POR internal VREG LVR Main VREG
Pulse Duration after reset event is removed
Figure 15. Internal Reset Routing
RESET SOURCE
High Temperature Reset The device is protected against high temperature. When the chip temperature exceeds a certain temperature, a reset (HTR) is generated. The reset is flagged by the HTR bit in the Interrupt Flag Register. A HTR event will reset all registers in the SPI excluding the RSR. The HTR can be disabled by bit HTRD in the Interrupt Mask register. Note: Disabling the high temperature reset can lead to destruction of the part in cases of high temperature. This bit was foreseen for test purposes only! Watchdog Reset The watchdog module generates a reset, because of a watchdog timeout or wrong watchdog timer reset. Reset is flagged by the WDR bit in the Reset Status Register. A watchdog reset event will reset all registers in the SPI excluding the RSR. Main VREG Low Voltage Reset The LVR is related to the Main VDD. If the voltage falls below a certain threshold, it will pull down the RST_A pin. Reset is flagged by the LVR bit in the Reset Status Register.
An LVR event will reset all register in the SPI excluding the RSR. Power On Reset The POR is related to the internal 5V supply. If the device detects a power on, the POR bit in the Reset Status Register (RSR) is set. A power on reset will reset all register in the SPI including the RSR and set the POR bit. The Power On Reset circuitry will force the RST_A pin low for tRST after the VDD has reached its nominal value (above LVR Threshold). Also see Figure 10, page 20). Reset Pin / External Reset An external reset can be applied by pulling down the RST_A pin. The reset event is flagged by the PINR bit in the reset status register. Reset Status Register This register contains five flags that shows the source of the last reset. A power-on-reset sets the POR bit and clears all other bits in the Reset Status Register. All bits can be cleared by writing a one to the corresponding bit. Uncleared bits remain set as long as they are not cleared by a poweron-reset or by software. In addition, the register includes two flags which will indicate the source of a wake-up from Sleep mode: Either LIN bus activity, or an event on the L0 wake-up input pin.
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HTR-- High Temperature Reset Bit This read/write bit is set if the chip temperature exceeds a certain value. The bit is cleared by writing a logic "1" to this location. 1 = reset due to high temperature condition 0 = no high temperature reset LVR-- Low Voltage Reset Bit This read/write bit is set if the external VDD voltage coming from the main voltage regulator falls below a certain value. The bit is cleared by writing a logic "1" to this location. 1 = reset due to low voltage condition 0 = no low voltage reset LINWF-- LIN Wake-up Flag This read/write bit is set if a bus activity was the case of an wake-up. The bit is cleared by writing a logic "1" to this location. 1 = Wake-up due to bus activity 0 = no wake-up due to bus activity L0WF-- L0 Wake-up Flag This read/write bit is set if a event on the L0 pin caused an wake-up. The bit is cleared by writing a logic "1" to this location. 1 = Wake-up due to L0 pin 0 = no Wake-up due to L0 pin
Register Name and Address: RSR - $0D Bit7
Read POR Write POR PINR WDR HTR LVR
6
5
4
3
2
0
1
Bit0
LINWF LOWF
1
0
0
0
0
0
0
0
POR-- Power On Reset bit This read/write bit is set after power on. Bit is cleared by writing a logic "1" to this location. 1 = Reset due to power on 0 = no power on reset PINR-- Reset Forced from External Reset Pin Bit This read/write bit is set after a reset was forced on the external reset RST_A pin. The bit is cleared by writing an logic "1" to this location. 1 = reset source is external reset pin 0 = no external reset WDR-- Watch Dog Reset Bit This read/write flag is set due to a watchdog timeout or wrong watchdog timer reset. Clear WDR by writing a logic "1" to WDR. 1 = reset source is watchdog 0 = no watchdog reset
ANALOG DIE INPUTS/OUTPUTS LIN PHYSICAL LAYER
The LIN bus pin provides a physical layer for single wire communication in automotive applications. The LIN physical layer is designed to meet the LIN physical layer specification. The LIN driver is a low side MOSFET with internal current limitation and thermal shutdown. An internal pullup resistor with a serial diode structure is integrated, so no external pullup components are required for the application in a slave node. The fall time from dominant to recessive and the rise time from recessive to dominant is controlled. The symmetry between both slew rate controls is guaranteed. The slew rate can be selected for optimized operation at 10 and 20kBit/s as well as high baud rates for test and programming. The slew rate can be adapted with 2 bits SRS[1:0] in the System Control Register. The initial slew rate is optimized for 20kBit/s. The LIN pin offers high susceptibility immunity level from external disturbance, guaranteeing communication during external disturbance. The LIN transmitter circuitry is enabled by setting the PSON bit in the System Control Register (SYSCTL). If the transmitter works in the current limitation region, the LINCL bit in the System Status Register (SYSSTAT) is set and the LIN transceiver is disabled after a certain time. For improved performance and safe behavior, in case of LIN bus short to Ground or LIN bus leakage during low power mode, the internal pullup resistor on the LIN pin is disconnected from VSUP and a small current source keeps the LIN bus at recessive level. In case of a LIN bus short to GND, this feature will reduce the current consumption in STOP and SLEEP modes.
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MODE
PSON
SRS[1:0]
VSUP
Wake-up
LINIF LINCL Control 10A
30k
LIN bus
TXD
Slope Control
TESTMODE
Wake-up Filter
GND
RXD
Figure 16. LIN Interface TXD Pin The TXD pin is the MCU interface to control the state of the LIN transmitter (see Figure 2, page 2). When TXD is LOW, the LIN pin is low (dominant state). When TXD is HIGH, the LIN output MOSFET is turned off (recessive state). The TXD pin has an internal pullup current source to set the LIN bus to a recessive state in the event, for instance, if the microcontroller could not control it during system power-up or power-down. RXD Pin The RXD transceiver pin is the MCU interface, which reports the state of the LIN bus voltage. LIN HIGH (recessive state) is reported by a high level on RXD, LIN LOW (dominant state) by a low level on RXD. STOP Mode and Wake-up Feature During STOP mode operation the transmitter of the physical layer is disabled and the internal pullup resistor is disconnected from VSUP and a small current source keeps the LIN pin in recessive state. The receiver is still active and able to detect wake-up events on the LIN bus line. If the LIN interrupt is enabled (LINIE bit in the Interrupt Mask register is set), a dominant level longer than TPROPWL A0 - Analog Input Input A0 is an analog input used for reading switches, or as analog inputs for potentiometers, NTC, etc. A0 is internally connected to the analog multiplexer. This pin offers a switchable current source. To read the Analog Input, the pin has to be selected with the SS[3:0] bits in the A0MUCTL register. followed by an rising edge will set the LINIF flag and generate an interrupt which causes a system wake-up (see Figure 8, page 19) SLEEP Mode and Wake-up Feature During SLEEP mode operation the transmitter of the physical layer is disabled, the internal pullup resistor is disconnected from VSUP, and a small current source keeps the LIN pin in the recessive state. The receiver is still active to be able to detect wake-up events on the LIN bus line. A dominant level longer than TPROPWL followed by an rising edge will generate a system wake-up (reset) and set the LINWF flag in the Reset Status register (RSR). Also see Figure 9, page 19).
Receiver
A0 INPUT AND ANALOG MULTIPLEXER
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Source Selection Bits SSx 4 VDD
CSSEL
Selectable Current Source
PSON
ADOUT
Analog Multiplexer
CSON
A0
SS[0:3]
Analog Port A0/A0CST
A0CST
1%
Figure 17. Analog Input and Multiplexer A0 Current Source The pin A0 provides a switchable current source, to be able to read in switches, NTC, etc., without the need of an additional supply line for the sensor. The overall enable of this feature is done by setting the PSON bit in the System Control register. In addition, the pin has to be selected with the SS[3:0] bits. The current source can be enabled with the CSON Bit and adjusted with the bits CSSEL[1:0]. With the CSSEL[1:0] bit's, four different current values can be selected (40, 120, 320 and 800A). This function is halted during STOP and SLEEP mode operations. The current source is derived from the VDD voltage, and is constant up to an output voltage of ~4.75V. connected. Switching the current sources to this resistor, allows the user to measure the current and use the measured value for calculating the current on A0. Analog Multiplexer / ADOUT pin The ADOUT pin is the analog output interface to the Analog-to-digital converter of the MCU. To be able to have different sources for the MCU with one single signal, an analog multiplexer is integrated in the analog die. This multiplexer has eleven different sources, which can be selected with the SS[3:0] bits in the A0MUCTL register. Half-bridge (HB1:HB4) Current Recopy The multiplexer is connected to the four current sense circuits on the low side FET of the half bridges. This sense circuits offers a voltage proportional to the current through the MOSFET. The resolution is depending on the CSA bit in the A0 and Multiplexer control register (A0MUCTL). High Side (HS1:HS3) Current Recopy The multiplexer is connected to the three high side switches. This sense circuit offers a voltage proportional to the current through the transistor. Analog Input A0 and A0CST A0 and A0CST are directly connected to the analog multiplexer. It offers the possibility to read analog values from the periphery.
IA0(UA0)
100%
4.75 5 To calibrate the current sources, an extra pin (A0CST) is envisioned. On this pin, an accurate resistor can to be
UA0[V]
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Temperature Sensor The analog die includes an on chip temperature sensor. This sensor offers a voltage which is proportional to the actual mean chip junction temperature. VSUP Prescaler The VSUP prescaler offers a possibility to measure the external supply voltage. The output of this voltage is VSUP / RATIOVSUP. A0 and Multiplexer Control Register (A0MUCTL)
SS[3:0] -- Analog Source Input Select Bits These read/write bits selects the analog input source for the ADOUT pin. Reset clears the SS[3:0] bits Analog Multiplexer Configuration Bits.
SS3
0 0 0 0
SS2
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
SS1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
SS0
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Channel
current recopy HB1 current recopy HB2 current recopy HB3 current recopy HB4 current recopy HS1 current recopy HS2 current recopy HS3 not used Chip temperature VSUP prescaler Pin A0 Pin A0CST not used not used not used not used
Register Name and Address: A0MUCTL - $08
0
Bit7 Read CSON Write Reset 0 6 5 4 3 2 1 Bit0
0 0 0
CSSEL 1
CSSEL 0
CSA
SS3
SS2
SS1
SS0
0
0
0
0
0
0
0
1 1 1 1 1 1 1 1
CSON -- Current Source on/off This read/write bit enables the current source for the A0 or A0CST inputs. Reset clears CSON bit. 1 = Current Source enabled 0 = Current Source disabled CSSEL[1:0] -- Current Source Select Bits These read/write bits select the current source values for A0 or A0CST input. Reset clears CSSEL[1:0] bits. Table 7. A0 Current Source Level Selection Bits
CSSEL1
0 0 1 1
CSSEL0
0 1 0 1
Current Source Enable (typ.)
40A 120A 320A 800A
Hall-effect Sensor Input Pin H0 The H0 pin can be configured as general purpose input (H0MS = 0) or as hall-effect sensor input (H0MS = 1) to be able to read 3pin / 2pin hall sensors or switches.
CSA -- H-bridges Current Sense Amplification Select Bit This read/write bit selects the current sense amplification of the H-Bridges HB1:HB4 current recopy. Reset clears the CSA bit. 1 = low current sense amplification 0 = high current sense amplification
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FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES
VDD
10k
H0PD
VSUP H0MS H0EN H0MS
H0F
H0
H0EN
Current Sense
Figure 18. General purpose / Hall-effect Sensor Input (H0) Current Coded Hallsensor Input H0 is selected as "2-pin hallsensor input", if the corresponding H0MS bit in the H0/L0 Status and Control Register (HLSCTL) is set. In this mode, the pin current to GND is monitored by a special sense circuitry. Setting the H0EN bit in the H0/L0 Status and Control Register, switches the output to VSUP and enables the sense circuitry. The result of the sense operation is given by the H0F flag. The flag is low if the sensed current is higher than the sense current threshold IHSCT. In this configuration, the HO pin is protected (current limitation) against short-circuit to GND. After switching on the hallport (H0EN = "1"), the hallsensor needs some time to stabilize the output. In RUN mode, the software has to take care about waiting for a few s (40) before sensing the hallflags. The hallport output current is sensed. In case of an overcurrent (short to GND), the hallport over-current flag (H0OCF) is set and the current is limited. For proper operation of the current limitation, an external capacitor (>100nF) close to the H0 pin is required.
VSUP
H0EN Current Sense H0
2 pin hall sensor
>0.1uF
H0F GND V
Figure 19. H0 Used as 2-pin Hallsensor Input
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General Purpose Input H0 is selected as a general purpose input, if the H0MS bit in the H0/L0 Status and Control Register (HLSCTL) is cleared. In this mode, the input is usable as a standard 5V
input. The H0 input has a selectable internal pullup resistor. The pullup can be switched off with the H0PD bit in the H0/L0 Status and Control Register (HLSCTL). After reset, the internal pullup is enabled.
VDD
VDD
3 pin hall sensor HVDD Vs
10k HVDDON H0PD H0F H0 OUT
GND
GND
Figure 20. H0 Used as 3 Pin Hall-effect Sensor Input
VDD
10k
H0PD H0F H0
GND
Figure 21. H0 Used to Read in Standard Switches H0 Interrupt The interrupt functionality on this pin is only available in RUN mode. The H0 interrupt flag H0IF is set in run mode by a state change of the H0 flag (rising or falling edge on the enabled input). The interrupt function is available if the input is selected as General Purpose or as 2-pin Hallsensor input. The interrupt can be masked with the H0IE bit in the interrupt mask register. Wake-up input L0 The device provides one wake-up capable input for reading VSUP or VDD related signals.
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RUN Mode The actual input state is reflected in the L0F bit of the H0/ L0 Status and Control register (HLSCTL). The L0 pin offers an interrupt capability on the rising and falling edge. The interrupt can be enabled with the L0IE bit in the Interrupt Mask register. STOP/SLEEP Mode During STOP and SLEEP mode, the pin can be used to wake-up the device. Before entering the STOP or SLEEP mode, the actual state of the input is stored. If the state is changing during in the STOP or SLEEP mode, a wake-up is initiated. H0 / L0 Status and Control Register (HLSCTL)
H0F -- H0 Flag Bit This read only flag reflects the state of the H0 input 1 = Hallport sensed high / current below threshold detected 0 = Hallport sensed low / current above threshold detected H0EN -- H0 Input 2-pin Hall-effect sensor Enable Bit This read/write bit enables the 2-pin hall-effect sensor sense circuitry. Reset clears H0EN bit. 1 = Hallport H0 is switched on and sensed 0 = Hallport H0 disabled H0PD -- Hallport Pullup Disable Bit This read/write bit disables the H0 Pullup resistor. Reset clears H0PD bit. 1 = Hallport pullup resistor on H0 disabled 0 = Hallport pullup resistor on H0 enabled
Bit0
Register Name and Address: HLSCTL - $07
Bit7 Read Write Reset 0 0 0 0 0 0 0 0 L0F 6 0 5 0
H0OCF
4
3 H0F
2
1
H0MS -- H0 Mode Select
H0EN H0PD H0MS
These read/write bits select the mode of the H0 input Reset clears H0MS bit. 1 = H0 is 2-pin hallsensor input 0 = H0 is general purpose input Half-bridge Outputs Outputs HB1:HB4 provide four low-resistive half-bridge output stages. The half-bridges can be used in H-bridge, high side or low side configurations. Reset clears all bits in the H-bridge Output Register (HBOUT) owing to the fact that all half-bridge outputs are switched off. HB1:HB4 output features * Short-circuit (over-current) protection on high side and low side MOSFETs * Current recopy feature (low side MOSFET) * Over-temperature protection * Over-voltage and under-voltage protection * Active clamp on low side MOSFET
L0F -- L0 Flag Bit This read only flag reflects the state of the L0 input 1 = L0 input high 0 = L0 input low H0OCF -- H0 Over-current Flag Bit This read/write flag is set at over-current condition on H0 during 2-pin hallsensor mode. Clear H0OCF by writing a logic [1] to H0OCF. Reset clears the H0OCF bit. 1 = over-current condition on H0 pin has occurred 0 = no over-current condition on H0 pin has occurred
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FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES
VSUP
On/Off
High Side Driver
Status
Charge Pump Over-temperature Protection Over-current Protection
PWM
Control
HBx
On/Off
Low Side Driver
Current Recopy Current Limitation Active Clamp Over-current Protection
Status
PWM
GND
Figure 22. Half-bridge Push-Pull Output Driver Half-bridge Control Each output MOSFET can be controlled individually. The general enable of the circuitry is done by setting PSON in the System Control Register (SYSCTL). The HBx_L and HBx_H bits form one half-bridge. It is not possible to switch on both MOSFETs in one half-bridge at the same time. If both bits are set, the high side MOSFET is in PWM mode. To avoid both MOSFETs (high side and low side) of one half-bridge being on at the same time, a break-before-make circuit exists. Switching the high side MOSFET on is inhibited as long as the potential between gate and VSS is not below a certain threshold. Switching the low side MOSFET on is blocked as long as the potential between gate and source of the high side MOSFET did not fall below a certain threshold.
HALF-BRIDGE OUTPUT REGISTER (HBOUT)
Register Name and Address: HBOUT - $01 Bit7 Read Write Reset
HB4_ H
6
HB4_ L
5
HB3_ H
4
HB3_ L
3
HB2_ H
2
HB2_ L
1
HB1_ H
Bit0
HB1_ L
0
0
0
0
0
0
0
0
HBx_H, HBx_L -- Half-bridge Output Switches These read/write bits select the output of each half-bridge output according to Table 8. Reset clears all HBx_H, HBx_L bits.
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Table 8. Half-bridge Configuration
HBx_H HBx_L Mode
0 0
0 1
Low side and high side MOSFET off High side MOSFET off, low side MOSFET on High side MOSFET on, low side MOSFET off High side MOSFET in PWM mode
1
0
The high temperature interrupts flag (HTIF) is cleared (and the outputs reenabled) by writing a "1" to the HTIF flag in the Interrupt Flag Register (IFR) or by a reset. Clearing this flag has no effect as long as a high temperature condition is present. If the HTI shutdown is disabled, a second threshold high temperature reset (HTR) will be used to turn off all power stages (HB (all Fet's), HS, HVDD, H0) in order to protect the device. Half-Bridge Over-current Protection
1
1
Half-bridge PWM mode The PWM mode is selected by setting both HBxL and HBxH of one half-bridge to "1". In this mode, the high side MOSFET is controlled by the incoming PWM signal on the PWM pin (see Figure 2, page 2). If the incoming signal is high, the high side MOSFET is switched on. If the incoming signal is low, the high side MOSFET is switched off. With the current recirculation mode control bit CRM in the Half-bridge Status and Control Register (HBSCTL), the recirculation behavior in PWM mode can be controlled. If CRM is set, the corresponding low side MOSFET is switched on, if the PWM controlled high side MOSFET is off. Half-bridge Current Recopy Each low side MOSFET has an additional sense output to allow a current recopy feature. These sense sources are internally amplified and switched to the Analog Multiplexer. The factor for the Current Sense amplification can be selected via the CSA bit in the A0MUCTL register (see page 33) CSA = "1": low resolution selected CSA = "0": high resolution selected
The Half-bridges are protected against short to GND, VSUP, and load shorts. The over-current protection is implemented on each HB. If an over-current condition on the high side MOSFET occurs, the high side MOSFET is automatically switched off. An over-current condition on the low side MOSFET will automatically turn off the low side MOSFET. In both cases, the corresponding HBxOCF flag in the Half-bridge Status and Control Register (HBSCTL) is set. The over-current status flag is cleared (and the corresponding half-bridge MOSFETs reenabled) by writing a "1" to the HBxOCF in the Half-bridge Status and Control Register (HBSCTL) or by a reset. Half-bridge Over-voltage/Under-voltage Protection The half-bridge outputs are protected against undervoltage and over-voltage conditions. This protection is done by the low and high voltage interrupt circuitry. If one of these flags (LVIF, HVIF) are set, the outputs are automatically disabled when the VIS bit in the System Control Register (SYSCTL) is cleared. The over-voltage and under-voltage status flags are cleared (and the outputs reenabled) by writing a "1" to the LVIF / HVIF flags in the Interrupt Flag Register (IFR), or by a reset. Clearing this flag has no effect as long as the high voltage or low voltage condition is still present. Half-bridge Status and Control Register (HBSCTL)
Register Name and Address: HBSCTL - $03
Half-bridge Over-temperature Protection The outputs are protected against over-temperature conditions. Each power output comprises two different temperature thresholds. The first threshold is the high temperature interrupt (HTI). If the temperature reaches this threshold, the HTIF bit in the Interrupt Flag Register (IFR) is set, and an interrupt will be initiated if the HTIE bit in the Interrupt Mask register is set. In addition, this interrupt can be used to automatically turn off the power stages. This shutdown can be enabled/disabled by the HTIS0-1 Bits in the System Control Register (SYSCTL).
Read
Bit7
6 0
5 0
4 0
3
2
1
Bit0
CRM Write Reset 0 0 0 0
HB4 OCF
0
HB3 OCF
0
HB2 OCF
0
HB1 OCF
0
CRM -- Current Recirculation Mode bit This read/write bit selects the recirculation mode during PWM. Reset clears the CRM bit. 1 = recirculation via switched on low side MOSFET 0 = recirculation via low side free wheeling diode
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Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES
HBxOCF -- Half-bridges Over-current Flag Bit This read/write bit indicates that an over-current condition on either the LS or the HS FET on HBx has occurred. Clear HBxOCF and enable half-bridge by writing a logic [1] to HBxOCF. Writing a logic [0] to HBxOCF has no effect. Reset clears the HBxOCF bit. 1 = over-current condition on HBx occurred 0 = no over-current condition on HBx
High Side Drivers The high side outputs are low resistive high side switches, targeted for driving lamps. The high sides are protected against over-temperature, over-current, and over-voltage/ under-voltage.
VSUP
PSON HSxON HSxPWM PWM
on/off
HS - Driver
charge pump over-current protection inrush current limiter PWM HSx
Control
Status Current Limit
Figure 23. HS Circuitry
HIGH SIDE OPERATING MODES
The high side outputs are enabled if the PSON bit in the System Control Register (SYSCTL) is set. Each high side output is permanently switched on, if the HSxON bit in the High Side Output Register (HSOUT) is set.
PWM control of the output is enabled, if the HSxPWM bit High Side Output Register (HSOUT) is set. In this operating mode, the high side MOSFET is on if the input PWM signal (PWM pin) is high. The following table shows the behavior of the high side MOSFETs depending on the HSONx and PWMHSx bits.
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Table 9. High Side Configuration Bits
HSxPWM 0 0 HSxON 0 1 Mode
High side MOSFET off High side MOSFET on if over-current, the over-current flag (HSxOCF) is set, and the High side MOSFET is turned off In this mode, the PWM duty cycle is either controlled by the PWM input signal, or if the over-current shutdown value is reached by the part itself. Without reaching the over-current shutdown, the high side driver is directly driven from the PWM input signal. If the Input signal is high, the output is on. If low, the output is off (PWM control). If the current reaches the over-current shutdown value, the high side will be automatically turned off. With the next rising edge of the PWM input signal, the output will turn on again (current limitation). The HSxOCF bit will be set. The software has to distinguish between an inrush current and a real short on the output.
The over /under-voltage status flags are cleared (and the output reenabled), by writing a logic [1] to the LVIF / HVIF flags in the Interrupt Flag Register, or by reset. Clearing this flag has no effect as long as a high or low voltage condition is present.
HIGH SIDE OVER-TEMPERATURE PROTECTION
The outputs are protected against over-temperature conditions. Each power output comprises two different temperature thresholds. The first threshold is the high temperature interrupt (HTI). If the temperature reach this threshold, the HTI bit in the interrupt flag register is set and an interrupt will be generated, if the HTIE bit in the interrupt mask register is set. In addition, this interrupt can be used to automatically turn off the power stages (all high sides, on Half-bridges just the high side FET's). This shutdown can be enabled/disabled by the HTIS0 bit. The high temperature interrupts flag (HTIE) is cleared (and the outputs reenabled) by writing a logic [1] to the HTIF flag in the Interrupt Status Register, or by reset. Clearing this flag has no effect as long as a high temperature condition is present. If the HTIS shutdown is disabled, a second threshold (HTR) will be used to turn off all power stages (HB (all Fet's), HS, HVDD, H0) in order to protect the device. High Side Over-current Protection The HS outputs are protected against over-current. When the over-current limit is reached, the output will be automatically switched off and the over-current flag is set. Due to the high inrush current of bulbs, a special feature was implemented to avoid a over-current shutdown during this inrush current. If a PWM frequency will be supplied to the PWM input during the switch on of a bulb, the inrush current will be limited to the over-current shutdown limit. This means, if the current reaches the over-current shutdown, the high side will be switched off, but each rising edge on the PWM input will enable the driver again. The duty cycle supplied by the MCU has no influence on the switch-on time of the high side driver. In order to distinguish between a shutdown due to an inrush current or a real shutdown, the software checks if the over-current status flag (HSxOCF) in the High Side Status register is set beyond a certain period of time.
1
0
1
1
High side MOSFET is switched on and the inrush current limitation is enabled. This means the high side will start automatically with a current limitation around the over-current shutdown threshold. (PWM signal must be applied, see Figure 24) If the high side enters current limitation, the HSxOCF bit is set, but the output is not disabled. The software needs to distinguish between an inrush current and a real short on the output.
High Side Over-voltage / Under-voltage Protection The outputs are protected against under /over-voltage conditions. This protection is done by the low and high voltage interrupt circuitry. If an over /under-voltage condition is detected (LVIF / HVIF), and Bit VIS in the High Side Status Register is cleared, the output is disabled.
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HS Current
HS Over-current Shutdown Threshold
t
PWM Pin
t
Figure 24. Inrush Current Limitation on HS Outputs High Side Current Recopy Each High Side has an additional sense output to allow a current recopy feature. This sense source is internally connected to a shunt resistor. The drop voltage is amplified and switched to the Analog Multiplexer. Switchable HVDD Outputs The HVDD pin is a switchable 5V output pin. It can be used for driving external circuitry, which requires a 5V voltage. The output is enabled with the PSON bit in the System Control register, and can be switched on / off with the HVDD_ON bit in the High Side Out register. Low or high voltage conditions (LVIF / HVIF) will have no influence on this circuitry. HVDD Over-temperature Protection The output is protected against over-temperature conditions. HVDD Over-current Protection The HVDD output is protected against over-current. In case the current reaches the over-current limit, the output current will be limited, and the HVDDOCF over-current flag in the System Status register is set.
Read Write Reset
HIGH SIDE OUT REGISTER (HSOUT)
Register Name and Address: HSOUT - $02
Bit7
HVDD ON 0
6
0
5
HS3P WM 0
4
HS2P WM 0
3
HS1P WM 0
2
HS3O N 0
1
HS2O N 0
Bit0
HS1O N 0
0
HVDD-ON -- HVDD On Bit This read/write bit enables the HVDD output. Reset clears HVDDON bit. 1 = HVDD enabled 0 = HVDD disabled HSxON -- High Side on/off Bits These read/write bits turn on the High Side Fet's permanently. Reset clears the HSxON bits. 1 = High Side x is turned on 0 = High Side x is turned off
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HSxPWM -- High Side PWM on/off Bits These read/write bits enable the PWM control of the High Side Fet's. Reset clears the HSxPWM bits. 1 = High Side x is controlled by PWM input signal 0 = High Side x is not controlled by PWM input signal High Side Status Register (HSSTAT)
0 = power stages disabled STOP -- Change to STOP Mode Bit This write bit instructs the chip to enter Stop mode (See Operational Modes on page 26). Reset or CPU interrupt requests clear the STOP bit. 1 = go to Stop mode 0 = not in stop mode In order to safely enter Stop mode, all other bits (Bit7-Bit2) have to be "0". Otherwise the STOP command will not execute. SLEEP -- Change to SLEEP Mode Bit
Register Name and Address: HSSTAT - $04
Bit7 Read Write Reset HVDD OCF 0 6 0 5 0 4 0 3 0 2 HS3O CF 0 1 HS2O CF 0 Bit0 HS1O CF 0
0
0
0
0
HSxOCF -- High Side Over-current Flag Bit This read/write flag is set by an over-current condition at the high side drivers x. Clear HSxOCF and enable the HS Driver by writing a logic [1] to HSxOCF. Writing a logic [0] to HSxOCF has no effect. Reset clears the HSxOCF bit. 1 = over-current condition on high side drivers has occurred 0 = no over-current condition on high side drivers has occurred HVDDOCF -- HVDD Output Over-current Flag Bit This read/write flag is set by an over-current condition at HVDD pin. Clear HVDDOCF and enable the output by writing a logic [1] to the HVDDOCF Flag. Writing a logic [0] to HVDDOCF has no effect. Reset clears the HVDDOCF bit. 1 = over-current condition on VDD output has occurred 0 = no over-current condition on VDD output has occurred System Control Register (SYSCTL)
This write bit instructs the chip to enter Sleep mode (See Operational Modes on page 26). Reset or CPU interrupt requests clear the SLEEP bit. 1 = go to Sleep mode 0 = not in sleep mode In order to safely enter Sleep mode all other bits (Bit7-Bit2) have to be "0". Otherwise the SLEEP command will not execute. HTIS0-1 -- High Temperature Interrupt Shutdown Bits This read/write bit selects the power stage behavior at High Temperature Interrupt (HTI). Reset clears the HTIS0-1 bits. The HTIS0 bit selects the behavior of the high side HS1:3 and the high side FET of the half-bridges HB1:4. 1 = automatic HTI shutdown of the high side drivers disabled 0 = automatic HTI shutdown of the high side drivers enabled The HTIS1 bit selects the behavior of the low side drivers of the half-bridges HB1:4. 1 = automatic HTI shutdown of the low side drivers disabled 0 = automatic HTI shutdown of the low side drivers enabled The user has to take care to protect the device against thermal destruction! VIS -- Over/Under-voltage Interrupt Shutdown This read/write bit selects the power stage behavior at LVI/ HVI. Reset clears the VIS bit. 1 = automatic LVI/HVI shutdown disabled 0 = automatic LVI/HVI shutdown enabled SRS0-1 -- LIN Slew Rate Select Bits These read/write bits enable the user to select the appropriate LIN slew rate for different Baudrate configurations. Reset clears the SRS1:0 bits.
Register Name and Address: SYSCTL - $00
Bit7 Read
PSON
6
0
5
0
4
3
2
VIS
1
SRS1
Bit0
SRS0
HTIS1 HTIS0 STOP SLEEP
Write Reset 0
0
0
0
0
0
0
0
PSON -- Power Stages On Bit This read/write bit enables the power stages (half-bridges, high sides, LIN transmitter, A0 Current Sources and HVDD output). Reset clears the PSON bit. 1 = power stages enabled
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Table 10. LIN Slew Rate Selection Bits
SRS1 SRS0 Slew rate
HVDDF-- HVDD Failure Bit This read only bit is a copy of the HVDDOCF bit in the High Side Status register 1 = HVDD pin fail 0 = HVDD normal operating HSF-- HS1:3 Failure Bit This read only bit is set if a fail condition on one of the high side outputs is present 1 = HS1:3 pin fail 0 = HS1:3 normal operating
0 0 1 1
0 1 0 1
Initial Slew Rate (20kBaud) High Speed II (8x) Slow Slew Rate (10kBaud) High Speed I (4x)
The high speed slew rates are used, for example, for programming via the LIN, and are not intended for use in the application. System Status Register (SYSSTAT)
HS1OCF
Register Name and Address: SYSSTAT - $0C
HS2OCF
Bit0 0
HSF
Bit7 Read Write Reset 0 LINC L
6 HTIF
5 VF
4 H0F
3 HVD DF
2 HSF
1 HBF
HS3OCF
Figure 26. HSF Flag Generation HBF-- HB1:4 Failure Bit
0
0
0
0
0
0
0
LINCL -- LIN Current Limitation Bit This read only bit is set if the LIN transmitter operates in current limitation region. Due to excessive power dissipation in the transmitter, the driver will be automatically turned off after a certain time. 1 = transmitter operating in current limitation region 0 = transmitter not operating in current limitation region HTIF-- Over-temperature Status Bit This read only bit is a copy of the HTIF bit in the Interrupt Flag register 1 = over-temperature condition 0 = no over-temperature condition VF -- Voltage Failure Bit This read only bit indicates that the supply voltage was out of the allowed range. The bit is set if either the LVIF or the HVIF in the Interrupt Flag register is set. 1 = low/high voltage condition detected 0 = no voltage failure condition detected
This read only bit is set if a fail condition on one of the halfbridge outputs is present. 1 = HB1:4 pin over-current fail 0 = HB1:4 normal operating
HB1OCF HB2OCF HB3OCF HB4OCF
Figure 27. HBF Flag Generation
HBF
WINDOW WATCHDOG
The window watchdog is used to supervise the device, and to recover from, e.g. code runaways, or similar conditions. The use of a window watchdog adds additional safety, as the watchdog clear has not only to occur, but be done at a certain time frame / window. Normal mode The window watchdog function is only available in Normal mode, and is halted in Stop and Sleep mode. On setting the WDRE bit, the watchdog functionality is activated. Once this function is enabled, it is not possible to disable it via software. Reset clears the WDRE bit. To prevent a Watchdog reset, the Watchdog timer has to be cleared in the Window Open frame. This is done by writing a logic "1" to the WDRST bit in the Watchdog Control register (WDCTL). The actual reset of the watchdog counter occurs at the end of the corresponding SPI transmission, with the rising edge of the SS signal.
HVIF LVIF
VF
Figure 25. VF Flag Generation H0F -- H0 Failure Bit This read only bit is a copy of the H0OCF bit in the H0/L0 Status and Control Register (HLSCTL) 1 = over-current detected on H0 0 = no over-current on H0
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If the watchdog is enabled, it will generate a system reset, if the timer has reached its end value, or if a watchdog reset (WDRST) has occurred in the closed window. The watchdog period can be selected with 2 bits in the WDCTL, in order to get 10ms, 20ms, 40ms and 80ms period.
WDP1:0 - Watchdog Period Select Bits This read/write bit select the clock rate of the Watchdog. Reset clears the WDP1:0 bits. Table 11. Watchdog Period Selection Bits
WDP1 WDP0 Mode
Window closed no watch dog clear allowed
Window open for watch dog clear
0 0 1
0 1 0 1
80ms window watchdog period 40ms window watchdog period 20ms window watchdog period 10ms window watchdog period
WD timing x 50%
WD timing x 50%
1
WDRST - Watchdog Reset Bit
WD period ( timing selected by Bits WDP1:0)
Figure 28. Window Watchdog Period Stop mode Operations of the watchdog function is halted in stop mode (counter/oscillator stopped). After wake-up, the watchdog timer is automatically cleared, in order to give the MCU the full time to reset the watchdog. Sleep mode Operations of the watchdog function is halted in sleep mode. Because the main voltage regulator asserts an LVR reset, the Watchdog functionality is disabled, and the WDRE bit is cleared as soon as sleep mode is entered. To re-enable this function bit WDRE has to be set after wake-up. Watchdog Control Register (WDCTL)
This write only bit resets the Watchdog. Write a logic [1] to reset the watchdog timer. 1 = Reset WD and restart timer 0 = no effect Voltage Regulator The 908E621 contains a low power, low drop voltage regulator, to provide internal power and external power for the MCU. The on-chip regulator consist of two elements, the main regulator and the low voltage reset circuit. The VDD regulator accepts an unregulated input supply and provides a regulated VDD supply to all digital sections of the device. The output of the regulator is also connected to the VDD pin to provide the 5.0V to the microcontroller. Run mode During RUN mode the main voltage regulator is on. It will provide a regulated supply to all digital sections. STOP mode
Register Name and Address: WDCTL - $0B
Bit7 Read Write Reset 0
WDRE
6
WDP1
5
WDP0
4
0
3
0
2
0
1
0
Bit0
0
WDRST
During STOP mode, the Stop mode regulator will take care of suppling a regulated output voltage. The Stop mode regulator has a limited output current capability. SLEEP mode In Sleep mode, the main voltage regulator external, VDD, is turned off and the LVR circuitry will force the RST_A pin low.
0
0
0
0
0
0
0
WDRE - Watchdog Reset Enable Bit This read/write (write once) bit activates the watchdog. The WDRE can only be set and can not be cleared by software. Reset clears the WDRE bit. 1 = Watchdog enabled 0 = Watchdog disabled
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FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS
LOGIC COMMANDS AND REGISTERS 908E621 SERIAL PHERIPHERAL INTERFACE (SPI)
The Serial Peripheral Interface (SPI) creates the communication link between the MCU and the analog die. The interface consists of four pins * MOSI - Master Out Slave In (internal pulldown) * MISO - Master In Slave Out * SPSCK - Serial Clock (internal pulldown) * SS - Slave Select (internal pullup) A complete data transfer via the SPI, consists of 2 bytes. The master sends address and data, the slave returns system status and the data of the selected address.
SS
Read/Write, Address, Parity
Data (Register write)
MOSI
R/W
A4
A3
A2
A1
A0
P
X
D7
D6
D5
D4
D3
D2
D1
D0
System Status Register
Data (Register read)
MISO
S7
S6
S5
S4
S3
S2
S1
S0
D7
D6
D5
D4
D3
D2
D1
D0
SPSCK
Rising edge of SPSCK Change MISO/MOSI Output Falling edge of SPSCK Sample MISO/MOSI Input Slave latch register address Slave latch data
Figure 29. SPI Protocol * During the inactive phase of SS, the new data transfer will be prepared. The falling edge on the SS line, indicates the start of a new data transfer (framing), and puts MISO in the low impedance mode. The first valid data are moved to MISO with the rising edge of SPSCK. * The MOSI, MISO will change data on a rising edge of SPSCK. * The MOSI, MISO will be sampled on a falling edge of SPSCK. * The data transfer is only valid, if exactly 16 sample clock edges are present in the active phase of SS. * After a write operation, the transmitted data will be latched into the register by the rising edge of SS. * Register read data is internally latched into the SPI at the time when the parity bit is transferred * SS high will force MISO to high impedance Master Address Byte A4 - A0 Includes the address of the desired register. R/W Includes the information, if it is a read or a write operation. * If R/W = 1 (read operation), the second byte of master contains no valid information, and the slave just transmits back register data. * If R/W = 0 (write operation), the master sends data to be written in the second byte, the slave sends concurrently contents of selected register prior to write operation, and the write data is latched in the SMARTMOS registers on rising edge of SS. Parity P Completes the total number of 1 bits of (R/W,A[4-0]) to an even number. e.g. (R/W,A[4-0]) = 100001 -> P0 = 0. The parity bit is only evaluated during a write operations and ignored for read operations. Bit X Not used Master Data Byte This byte includes data to be written, or no valid data, during a read operation.
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FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS
Slave Status Byte This byte always includes the contents of the system status register ($0C), independent if it is a write or read operation, or which register was selected.
Slave Data Byte This byte includes the contents of selected register, during a write operation, it includes the register content prior to the write operation.
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SPI REGISTER OVERVIEW TABLE 12 SUMMARIZES THE SPI REGISTER ADDRESSES AND THE BIT NAMES OF EACH REGISTER.
Table 12. SPI Register Overview
Addr Register Name R/W Bit 7 6 5 4 3 2 1 0
$00
System Control (SYSCTL) Half-bridge Output (HBOUT) High Side Output (HSOUT) Half-bridge Status and Control (HBSCTL) High Side Status and Control (HSSCTL)
R W R W R W R W R W R HVDDOCF CRM HVDDON HB4_H PSON
0 STOP HB4_L 0
0 HTIS1 SLEEP HB3_H HB3_L HB2_H HB2_L HB1_H HB1_L HTIS0 VIS SRS1 SRS0
$01
$02
HS3PWM 0 0
HS2PWM 0
HS1PWM
HS3ON
HS2ON
HS1ON
$03
HB4OCF 0 0 0 0
HB3OCF
HB2OCF
HB1OCF
$04
HS3OCF
HS2OCF
HS1OCF
$05
Reserved
W R
reserved
$06
Reserved H0/L0 Status and Control (HLSCTL) A0 and Multiplexer Control (A0MUCTL) Interrupt Mask (IMR) Interrupt Flag (IFR) Watchdog Control (WDCTL) System Status (SYSSTAT) Reset Status (RSR) System Test (SYSTEST) System Trim 1 (SYSTRIM1) System Trim 2 (SYSTRIM2)
W R W R CSON W R W R W R W R W R W R W R W R W R W HVDDT1 0 HVDDT0 0 reserved 0 CRHB5 0 CRHS5 POR PINR WDR WDRE LINCL WDP1 HTIF WDP0 L0IF H0IF LINIF 0 0 L0IE H0IE LINIE CSSEL1 CSSEL0 L0F 0 0
reserved H0F H0OCF H0EN H0PD H0MS
$07
$08
CSA
SS3
SS2
SS1
SS0
$09
HTRD
HTIE
LVIE
HVIE
PSFIE PSFIF
$0A
HTIF 0
LVIF 0
HVIF 0 0 WDRST
$0B
VF
H0F
HVDDF
HSF
HBF
0
$0C
0 HTR LVR LINWF L0WF
$0D
$0E
reserved
$0F
reserved 0 CRHB4 0 CRHS4
itrim3 0 CRHB3 0 CRHS3
itrim2 0 CRHB2 0 CRHS2
itrim1 0 CRHB1 0 CRHS1
itrim0 0 CRHB0 0 CRHS0
$10
CRHBHC1 CRHBHC0 0 0
$11
System Trim 3 (SYSTRIM3)
CRHBHC3 CRHBHC2
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FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS
FACTORY TRIMMING AND CALIBRATION
To enhance the ease-of-use of the 908E621, various parameters (e.g. ICG trim value) are stored in the flash memory of the device. The following flash memory locations are reserved for this purpose and might have a value different from the "empty" ($FF) state: * $FD80:$FDDF Trim and Calibration Values * $FFFE:$FFFF Reset Vector In the event the application uses these parameters, one has to take care not to erase or override these values. If these parameters are not used, these flash locations can be erased and otherwise used. Trim Values The usage of the trim values located in the flash memory are explained through the following: Internal Clock Generator (ICG) Trim Value The internal clock generator (ICG) module is used to create a stable clock source for the microcontroller without using any external components. The untrimmed frequency of the low frequency base clock (IBASE), will vary as much as 25 percent due to process, temperature, and voltage dependencies. To compensate these dependencies, an ICG trim value is located at address $FDC2. After trimming, the ICG has a typ. range of 2% (3% max.), at nominal conditions (filtered (100nF), stabilized (4,7F) VDD = 5V, TAmbient~25C), and will vary over temperature and voltage (VDD) as indicated in the 68HC908EY16 datasheet. To trim the ICG, this value has to be copied to the ICG Trim Register ICGTR at address $38 of the MCU. Important: The value must be copied after every reset. Table 13. Window Clear Interval
Window Range Period Select bits $FDCF WDP1:0 Watchdog Period t_wd min. max. Unit Effective Open Window t_open t_closed Unit Optimal Clear Interval t_opt Unit max. variation
Watchdog Period Range Value (AWD Trim) The window watchdog supervises device recovery (e.g. from code runaways). The application software has to clear the watchdog within the open window. Due to the high variation of the watchdog period, and therefore the reduced width of the watchdog window, a value is stored at address $FDCF. This value classifies the watchdog period into 3 ranges (Range 0, 1, 2). This allows the application software to select one of three time intervals to clear the watchdog, based on the stored value. The classification is done, so that the application software can have up to 19% variations of the optimal clear interval (e.g. caused by ICG variation). Effective Open Window Having a variation in the watchdog period in conjunction with a 50% open window, results in an effective open window, which can be calculated by: latest window open time: t_open = t_wd max / 2 earliest window closed time: t_closed = t_wd min Optimal Clear Interval The optimal clear interval, meaning the clear interval with the biggest possible variation to latest window open time, and to the earliest window closed time, can be calculated with the following formula: t_opt = t_open + (t_open+t_closed) / 2 See Table 13 to select the optimal clear interval for the watchdog based on the Window No. and chosen period.
00 01 0 10 11 00 01 1 10 11 00 01 2 10 11
68 34 17 8.5 92 46 23 11.5 52 26 13 6.5
92 46 ms 23 11.5 124 62 ms 31 15.5 68 34 ms 17 8.5
46 23 11.5 5.75 62 31 15.5 7.75 34 17 8.5 4.25
68 34 ms 17 8.5 92 46 ms 23 11.5 52 26 ms 13 6.5
57 28.5 ms 14.25 7.125 77 38.5 ms 19.25 9.625 43 21.5 ms 10.75 5.375 20.9% 19.5% 19.3%
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Analog Die System Trim Values For improved application performance, and to ensure the outlined datasheet values, the analog die needs to be trimmed. For this purpose, 3 trim values are stored in the Flash memory at addresses $FDC4 - $FDC6. These values have to be copied into the analog die SPI registers: * copy $FDC4 into SYSTRIM1 register $0F * copy $FDC5 into SYSTRIM2 register $10 * copy $FDC6 into SYSTRIM3 register $11 Note: These values must be copied to the respective SPI register after a reset, to ensure proper trimming of the device. System Test Register (SYSTEST)
ITRIM3:0 - IRef Trim Bits These write only bits are for trimming the internal current references IRef (also A0, A0CST). The provided trim values have to be copied into these bits after every reset. Reset clears the ITRIM3:0 bits. Table 15. IRef Trim Bits
itrim3 itrim2 itrim2 itrim0 Adjustment
0 0 0 0
0 0 0 0 1 1 1 1 0
0 0 1 1 0 0 1 1 0
0 1 0 1 0 1 0 1 0
0 2% 4% 8% 12% -2% -4% -8% -12%
Register Name and Address: SYSTEST - $0E
Bit7 Read
reserved
6
reserved
5
reserved
4
reserved
3
reserved
2
reserved
1
reserved
Bit0
reserved
0 0 0
Write Reset 0 0 0 0 0 0 0 0
Note: do not write to the reserved bits
0 1
The System Test Register is reserved for production testing and is not allowed to be written to. System Trim Register 1 (SYSTRIM1)
System Trim Register 2 (SYSTRIM2)
Register Name and Address: IFBHBTRIM - $10 Register Name and Address: IBIAS - $0F
Bit7 1 Bit0
ITRIM0
6
0
CRHBHC0
5
0 CRHB5
4
0 CRHB4
3
0 CRHB3
2
0 CRHB2
1
0
Bit0
0
Bit7 Read
HVDDT1
6
HVDDT0
5
0
reserved
4
0
reserved
3
ITRIM3
2
ITRIM2
Read Write
0
CRHBHC1
CRHB1 CRHB0
ITRIM1
Write Reset 0 0
Reset 0 0 0 0
0
0
0
0
0
0
0
0
0
0
Note: do not change (set) the reserved bits
CRHBHC1:0 - Current Recopy HB1:2 Trim Bits These write only bits are for trimming the current recopy of the half-bridge HB1 and HB2 (CSA=0). The provided trim values have to be copied into these bits after every reset. Reset clears the CRHBHC1:0 bits. Table 16. Current Recopy Trim for HB1:2 (CSA=0)
CRHBHC1 CRHBHC0 Adjustment
HVDDT1:0 - HVDD Over-current Shutdown Delay Bits These read/write bits allow changes to the filter time (for capacitive load) for HVDD over-current detection. Reset clears the HVDDT1:0 bits and sets the delay to the maximum value. Table 14. HVDD Over-current Shutdown Selection Bits
HVDDT1 HVDDT0 Typical Delay
0 0 1 1
0 1 0 1
0 -10% 5% 10%
0 0 1 1
0 1 0 1
950s 536s 234s 78s
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FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS
CRHB5:3 - Current Recopy HB3:4 Trim Bits These write only bits are for trimming the current recopy of the half-bridge HB3 and HB4 (CSA=1). The provided trim values have to be copied into these bits after every reset. Reset clears the CRHB5:3 bits. Table 17. Current Recopy Trim for HB3:4 (CSA=1)
CRHB5 CRHB4 CRHB3 Adjustment
System Trim Register 3 (SYSTRIM3)
Register Name and Address: IFBHSTRIM - $11
Bit7 Read Write Reset
0 CRHBH C3
6
0 CRHBH C2
5
0 CRHS5
4
0 CRHS4
3
0 CRHS3
2
0 CRHS2
1
0 CRHS1
Bit0
0 CRHS0
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
0 -5% -10% -15% reserved
0
0
0
0
0
0
0
0
CRHBHC3:2 - Current Recopy HB3:4 Trim Bits These write only bits are for trimming the current recopy of the half-bridge HB3 and HB4 (CSA=0). The provided trim values have to be copied into these bits after every reset. Reset clears the CRHBHC3:2 bits. Current Recopy Trim for HB3:4 (CSA=0)
5%
CRHBHC3 CRHBHC2 Adjustment
10% 0 15% 0 1 0 1 -10% 5% 10% 0 0
CRHB2:0 - Current Recopy HB1:2 Trim Bits These write only bits are for trimming the current recopy of the half-bridge HB1 and HB2 (CSA=1). The provided trim values have to be copied into these bits after every reset. Reset clears the CRHB2:0 bits. Table 18. Current Recopy Trim for HB1:2 (CSA=1)
CRHB2 CRHB1 CRHB0 Adjustment
1 1
CRHS5:3 - Current Recopy HS2:3 Trim Bits These write only bits are for trimming the current recopy of the high side HS2 and HS3. The provided trim values have to be copied into these bits after every reset. Reset clears the CRHS5:3 bits. Table 19. Current Recopy Trim for HS2:3
CRHS5 CRHS4 CRHS3 Adjustment
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
0 -5% -10% 0 -15% 0 reserved 0 5% 0 10% 1 15% 1 1 1 0 1 1 1 0 1 5% 10% 15% 0 0 reserved 1 1 -15% 1 0 -10% 0 1 -5% 0 0 0
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FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS
CRHS2:0 - Current Recopy HS1 Trim Bits These write only bits are for trimming the current recopy of the high side HS1. The provided Trim values have to be copied into these bits after every reset. Reset clears the CRHS2:0 bits. Current Recopy Trim for HS1
CRHS2 CRHS1 CRHS0 Adjustment
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
0 -5% -10% -15% reserved 5% 10% 15%
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TYPICAL APPLICATIONS
TYPICAL APPLICATIONS
DEVELOPMENT SUPPORT
As the 908E621 has the MC68HC908EY16 MCU embedded, typically all the development tools available for the MCU also apply for this device. However, due to the additional analog die circuitry and the nominal +12V supply voltage, some additional items have to be considered: * nominal 12V rather than the 5V or 3V supply * high voltage VTST might be applied not only to IRQ pin, but IRQ_A pin * MCU monitoring (Normal request timeout) has to be disabled For a detailed information on the MCU related development support, see the MC68HC908EY16 datasheet section development support.
The programming is principally possible at two stages in the manufacturing process, first on chip level, before the IC is soldered onto a pcb board, and second after the IC is soldered onto the pcb board. Chip level programming At the Chip level, the easiest way is to only power the MCU with +5V (see Figure 30), and not to provide the analog chip with VSUP. In this setup, all the analog pins should be left open (e.g. VSUP[1:8]), and interconnections between the MCU and analog die have to be separated (e.g. IRQ - IRQ_A). This mode is well described in the MC68HC908EY16 datasheet, section development support.
VSUP[1:8] GND[1:4]
VDD VSS +5V VDDA/VREFH
RST EVDD RST_A +5V 1 1F + 3 4 1F + 5 C1C2+ GND V+ V15 2 6 1F + 74HC125 7 T2OUT 8 R2IN T2IN 10 74HC125 3 R2OUT 9 2 1 5 3 6 4 5 10k 10k DATA PTA1/KBD1 PTA0/KBD0 10k PTB3/AD3 + 9.8304MHz CLOCK +5V CLK PTC4/OSC1 PTB4/AD4 TESTMODE 10k 16 + 1F 1F VTST IRQ IRQ_A VSSA/VREFL 100nF 4.7F
C1+
VCC
MM908E621
EVSS +5V
MAX232
C2-
RS232 DB-9
2
Figure 30. Normal Monitor Mode Circuit (MCU only) Of course it is also possible to supply the whole system PCB level programming with VSUP instead (12V) as described in Figure 31, page 55. If the IC is soldered onto the pcb board, it is typically not possible to separately power the MCU with +5V. The whole system has to be powered up providing VSUP (see Figure 31).
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TYPICAL APPLICATIONS
.
VDD VSUP + 47F 100nF VSUP[1:8] GND[1:4] VDD VSS
VDDA/VREFH RST EVDD RST_A VDD 1 1F + 3 4 1F + 5 C1C2+ GND V+ V15 2 6 1F + 74HC125 7 T2OUT 8 R2IN T2IN 10 74HC125 3 R2OUT 9 2 1 5 3 6 4 5 10k 10k DATA PTA1/KBD1 PTA0/KBD0 10k PTB3/AD3 + 10k 9.8304MHz CLOCK VDD CLK PTC4/OSC1 PTB4/AD4 TESTMODE 10k 16 + 1F 1F VTST IRQ IRQ_A VSSA/VREFL 100nF 4.7F
C1+
VCC
MM908E621
EVSS VDD
MAX232
C2-
RS232 DB-9
2
Figure 31. Normal Monitor Mode Circuit Table 20 summarizes the possible configurations and the necessary setups. Table 20. Monitor Mode Signal Requirements and Options
Serial Communication
PTA0 Normal Monitor
Mode
IRQ RST TESTMODE
Reset Vector
Mode Selection ICG COP PTB3
0
PTA1
0
PTB4
1 OFF disabled
Communication Speed Normal Request Baud Bus Time-out External Clock Frequency Rate
disabled 9.8304 MHz 9.8304 MHz -- 2.4576 MHz 2.4576 MHz Nominal 1.6MHz Nominal 1.6MHz 9600
VTST VDD
VDD
1
X
1
OFF VDD 1 $FFFF (blank) 1 0 X X ON not $FFFF (not blank)
disabled
disabled
9600 Nominal 6300 Nominal 6300
Forced Monitor GND
disabled
disabled
User
VDD
VDD
0
X
X
X
X
ON
enabled
enabled
--
Notes 33. PTA0 must have a pullup resistor to VDD in monitor mode 34. 35. 36. 37. External clock is a 4.9152MHz, 9.8304MHz or 19.6608MHz canned oscillator on OCS1 Communication speed with external clock is depending on external clock value. Baud rate is bus frequency / 256 X = don't care VTST is a high voltage VDD + 3.5V VTST VDD + 4.5V
EMC/EMI RECOMMENDATIONS
This paragraph gives some device specific recommendations to improve EMC/EMI performance. Further generic design recommendations can be found on the Freescale web site www.freescale.com.
VSUP Pins (VSUP[1:8]) It is recommended to place a high quality ceramic decoupling capacitor close to the VSUP pins to improve EMC/EMI behavior.
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TYPICAL APPLICATIONS
LIN Pin For DPI (Direct Power Injection) and ESD (Electrostatic Discharge), it is recommended to place a high quality ceramic decoupling capacitor near the LIN pin. An additional varistor will further increase the immunity against ESD. A ferrite in the LIN line will suppress some of the noise induced. Voltage Regulator oUtput Pins (VDD and VSS) Use a high quality ceramic decoupling capacitor to stabilize the regulated voltage. MCU Digital Supply Pins (EVDD and EVSS) Fast signal transitions on MCU pins place high, short duration current demands on the power supply. To prevent
D1 VSUP + C1 C2 VSUP[1:8]
noise problems, take special care to provide power supply bypassing at the MCU. It is recommended that a high quality ceramic decoupling capacitor be placed between these pins. MCU aNalog Supply Pins (VREFH/VDDA and VREFL/ VSSA) To avoid noise on the analog supply pins, it is important to take special care on the layout. The MCU digital and analog supplies should be tied to the same potential via separate traces, and connected to the voltage regulator output. Figure 32 and Figure 33 show the recommendations on schematics and layout level, and Table 21 indicates recommended external components and layout considerations.
VDD VSS
L1 LIN V1 C5 LIN
VDDA/VREFH EVDD
C3
C4
MM908E621
GND[1:4]
EVSS
VSSA/VREFL
Figure 32. EMC/EMI recommendations
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TYPICAL APPLICATIONS
1 2 3 4 5 6 7 8 9 10 11 12 13 LIN VSS VDD VDDA/VREFH EVDD EVSS VSSA/VREFL
54 53 52 51 50 49 48 47
C3
46 45 44 43 42 41 40
C5
14 15 16 17 18 19 20 21 22 23 24 25 26 27
908E621
GND1
39 38
VSUP1 GND2
VSUP8
37 36
VSUP7 VSUP2
35 34 33
C4
GND C2 C1
VSUP6 VSUP5 GND3 GND4
32 31 30 29
VSUP3
VSUP4
28
D1
VBAT
V1
L1
LIN
Figure 33. PCB Layout Recommendations . Table 21. Component Value Recommendation
Component Recommended Value(1) Comments / Signal routing
D1 C1 C2 C3 Bulk Capacitor 100nF, SMD Ceramic, Low ESR 100nF, SMD Ceramic, Low ESR
reverse battery protection
Close to VSUP pins with good ground return Close (<3mm) to digital supply pins (EVDD, EVSS) with good ground return. The positive analog (VREFH/ VDDA) and the digital (EVDD) supply should be connected right at the C3.
C4 C5
4,7F, SMD Ceramic, Low ESR 180pF, SMD Ceramic, Low ESR
Bulk Capacitor Close (<5mm) to LIN pin. Total Capacitance on LIN has to be below 220pF. (Ctotal = CLIN-Pin + C5 + CVaristor ~ 10pF + 180pF + 15pF)
V1
(2)
Varistor Type TDK AVR-M1608C270MBAAB SMD Ferrite Bead Type TDK MMZ2012Y202B
Optional (close to LIN connector) Optional, (close to LIN connector)
L1(2)
Notes 1. Freescale does not assume liability, endorse, or want components from external manufactures that are referenced in circuit drawings or tables. While Freescale offers component recommendations in this configuration, it is the customer's responsibility to validate their application. 2. Components are recommended to improve EMC and ESD performance.
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PACKAGE DIMENSIONS
PACKAGE DIMENSIONS
Important For the most current revision of the package, visit www.freescale.com and do a keyword search on the 98A drawing number: 98ASA10712D.
DWB SUFFIX 54-PIN SOICW-EP 98ASA10712D ISSUE 0
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PACKAGE DIMENSIONS
DWB SUFFIX 54-PIN SOICW-EP 98ASA10712D ISSUE 0
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PACKAGE DIMENSIONS
DWB SUFFIX 54-PIN SOICW-EP 98ASA10712D ISSUE 0
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ADDITIONAL INFORMATION THERMAL ADDENDUM (REV 1.0)
ADDITIONAL INFORMATION
THERMAL ADDENDUM (REV 1.0) INTEGRATED QUAD H-BRIDGE AND TRIPLE HIGH-SIDE DRIVER WITH EMBEDDED MCU AND LIN FOR MIRROR
Introduction This thermal addendum is provided as a supplement to the MM908E621 technical data sheet. The addendum provides thermal performance information that may be critical in the design and development of system applications. All electrical, application and packaging information is provided in the data sheet. Package and Thermal Considerations This MM908E621 is a dual die package. There are two heat sources in the package independently heating with P1 and P2. This results in two junction temperatures, TJ1 and TJ2, and a thermal resistance matrix with RJAmn. For m, n = 1, RJA11 is the thermal resistance from Junction 1 to the reference temperature while only heat source 1 is heating with P1. For m = 1, n = 2, RJA12 is the thermal resistance from Junction 1 to the reference temperature while heat source 2 is heating with P2. This applies to RJ21 and RJ22, respectively. TJ1 TJ2
=
908E621
54-PIN SOICW-EP
DWB SUFFIX 98ARL105910 54-PIN SOICW-EP Note For package dimensions, refer to the 908E621 device datasheet.
RJA11 RJA12 RJA21 RJA22
.
P1 P2
The stated values are solely for a thermal performance comparison of one package to another in a standardized environment. This methodology is not meant to and will not predict the performance of a package in an application-specific environment. Stated values were obtained by measurement and simulation according to the standards listed below. Standards Table 22. Thermal Performance Comparison
1 = Power Chip, 2 = Logic Chip [C/W] Thermal Resistance
m = 1, n=1 m = 1, n = 2 m = 2, n = 1 m = 2, n=2
1.0 1.0 0.2
RJAmn (1)(2) RJBmn (2)(3) RJAmn (1)(4) RJCmn (5)
23 9.0 52 1.0
20 6.0 47 0
24 10 52 2.0
0.2 * All measurements are in millimeters Soldermast openings Thermal vias connected to top buried plane
Notes: 1. Per JEDEC JESD51-2 at natural convection, still air condition. 2. 2s2p thermal test board per JEDEC JESD51-7and JESD51-5. 3. Per JEDEC JESD51-8, with the board temperature on the center trace near the power outputs. 4. Single layer thermal test board per JEDEC JESD51-3 and JESD51-5. 5. Thermal resistance between the die junction and the exposed pad, "infinite" heat sink attached to exposed pad.
54 Terminal SOIC-EP 0.65 mm Pitch 17.9 mm x 7.5 mm Body 10.3 mm x 5.1 mm Exposed Pad Figure 34. Thermal Land Pattern for Direct Thermal Attachment Per JEDEC JESD51-5
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ADDITIONAL INFORMATION THERMAL ADDENDUM (REV 1.0)
PTC4/OSC1 PTC3/OSC2 PTC2/MCLK PTB5/AD5 PTB4/AD4 PTB3/AD3
IRQ RST
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
54 53 52 51 50 49 48 47 46 45 44 43 42
(PTD0/TACH0/BEMF -> PWM) PTD1/TACH1
RST_A IRQ_A
LIN A0CST A0 GND1 HB4 VSUP1 GND2 HB3 VSUP2 NC NC TESTMODE GND3 HB2 VSUP3
Exposed Pad
41 40 39 38 37 36 35 34 33 32 31 30 29 28
PTA0/KBD0 PTA1/KBD1 PTA2/KBD2 FLSVPP PTA3/KBD3 PTA4/KBD4 VDDA/VREFH EVDD EVSS VSSA/VREFL (PTE1/RXD <- RXD) VSS VDD HVDD L0 H0 HS3 VSUP8 HS2 VSUP7 HS1b HS1a VSUP6 VSUP5 GND4 HB1 VSUP4
A
908E621 Pin Connections
54-Pin SOICW-EP 0.65 mm Pitch 17.9mm x 7.5mm Body 10.3mm x 5.1mm Exposed Pad
Figure 35. Thermal Test Board Device on Thermal Test Board Material: Single layer printed circuit board FR4, 1.6mm thickness Cu traces, 0.07mm thickness 80mm x 100mm board area, including edge connector for thermal testing Cu heat-spreading areas on board surface Natural convection, still air Table 23. Thermal Resistance Performance
1 = Power Chip, 2 = Logic Chip (C/W) Thermal Resistance
Area A (mm2)
0 300 600
m = 1, n=1
m = 1, n = 2 m = 2, n = 1
m = 2, n=2
Outline:
RJAmn
53 39 35 21 15 14
48 34 30 16 11 9.0
53 38 34 20 15 13
Area A: Ambient Conditions:
RJSmn
0 300 600
RJA is the thermal resistance between die junction and ambient air. RJSmn is the thermal resistance between die junction and the reference location on the board surface near a center lead of the package. This device is a dual die package. Index m indicates the die that is heated. Index n refers to the number of the die where the junction temperature is sensed.
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Analog Integrated Circuit Device Data Freescale Semiconductor
ADDITIONAL INFORMATION THERMAL ADDENDUM (REV 1.0)
60 Thermal Resistance [C/W] 50 40 30 20
x
10 0
RJA11 RJA22 RJA12 = RJA21
0
Heat spreading area A [mm]
300
600
Figure 36. Device on Thermal Test Board RJA
100
Thermal Resistance [C/W]
10
1
x
0.1 1.00E-03
RJA11 RJA22 RJA12 = RJA21
1.00E-02
1.00E-01 1.00E+00 1.00E+01 1.00E+02 1.00E+03 1.00E+04
Time[s]
Figure 37. Transient Thermal Resistance RJA (1.0W Step Response) Device on Thermal Test Board Area A = 600(mm2)
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REVISION HISTORY
REVISION HISTORY
REVISION
DATE
DESCRIPTION OF CHANGES
3.0
2/2007
* *
* * 4.0 5.0 6/2007 6/2008 * * * * * * *
Implemented Revision History page Changed Table 3, Statistic Electrical Characteristics, Hall-Effect Sensor Input H0 - 2pin Hall Sensor Input Mode (H0MS = 1), Sense Current Hysteresis on page 14 from a Minimum of 800 to 600 and Typical from 1100 to none. Removed "Advance" watermark and updated to final Data Sheet. Removed Peak Package Reflow Temperature During Reflow (solder reflow) parameter from Electrical Characteristics on page 6. Added note with instructions from www.freescale.com. Updated to Final by removing "Advance Information" from page 1. Changed STOP Mode Total Output Current on page 9 from 850 to 1100A Changed Sense Current Hysteresis on page 14 from 800 to 650A Changed Normal Request Timeout on page 16 from 124 to 150ms Updated Freescale form and style to the current format Updated package drawing Added Functional Internal Block Description section
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Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals", must be validated for each customer application by customer's technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. FreescaleTM and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. (c) Freescale Semiconductor, Inc., 2007-2008. All rights reserved.
MM908E621 Rev. 5.0 6/2008

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